Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2003-04-07
2004-06-29
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S724000
Reexamination Certificate
active
06756664
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packaged chip or die with a noise-suppressing system. More particularly, the present invention relates to a noise-suppressing system, which is electrically connected to a chip, capable of reducing or eliminating excess noise.
2. Description of the Prior Art
Please refer to FIG.
1
.
FIG. 1
illustrates a cross section of a conventional leadframe package structure
10
mounted on a printed circuit board
11
. The printed circuit board
11
comprises an upper surface
12
and a lower surface
13
. For a four-layer printed circuit board
11
, the upper surface
12
and the lower surface
13
may be one of the power supply layer, grounded layer, signal layer, or device layer. Passive components
14
and
15
are mounted on either upper surface
12
or lower surface
13
by surface mount technology (SMT) known in the art. For example, the passive components
14
and
15
may be de-coupling capacitors used to reduce or eliminate undesired coupling between circuits or simultaneous switching noise (SSN) between the power supply layer and the grounded layer of a high-frequency circuit.
Please refer to FIG.
2
.
FIG. 2
is a cross-sectional view of a prior art ball grid array (BGA) package
20
. As shown in
FIG. 2
, a trace
22
is provided in a substrate
21
of the BGA package
20
. A chip
23
is mounted on the substrate
21
and is connected with the trace
22
of the substrate
21
via a wire bonding
24
. A passive component
14
is mounted on an upper surface of the substrate
21
by SMT. The chip
23
and the passive component
14
on the substrate
21
are encapsulated with encapsulant
25
. Again, the passive component
14
may be a de-coupling capacitor used to reduce or eliminate undesired coupling between circuits or SSN between the power supply layer and the grounded layer of a high-frequency circuit.
Typically, the de-coupling capacitor is preferably mounted in the proximity of the chip
23
to enhance the performance of the de-coupling capacitor to reduce SSN of the chip
23
. However, as the prior art examples shown in FIG.
1
and
FIG. 2
, the chip
23
and the de-coupling capacitor(s) are rested on the substrate
21
or the printed circuit board
11
. In such case, referring to
FIG. 3
, the efficiency of the de-coupling capacitor is reduced by the accumulated inductance and resistance in the coupling path. This causes a significant performance reducing of the de-coupling capacitor. Further, with reference to
FIG. 1
, in practice, the passive components
14
and
15
occupy a portion of the area of the upper surface
12
or the lower surface
13
of the printed circuit board
11
. With reference to
FIG. 2
, the passive component
14
is disposed on the substrate
21
. Under the above-described circumstance, when the number of the passive components
14
and
15
increases, there will be no more capacity for additional bonding route or other devices on the printed circuit board
11
or on the substrate
21
. In other words, the prior art packaging geometry limits the possibility of shrinking the dimension of the printed circuit board
11
or the substrate
21
.
Thus, there is a strong need for an improved chip package, which is reliable, cost-effective and is capable of effectively eliminating SSN.
SUMMARY OF THE INVENTION
Accordingly, the main object of the invention is to provide an improved chip package in combination with a noise-eliminating system and a fabrication method thereof to solve the above-mentioned problems. The noise eliminating system is mounted on the upper surface of the chip, such that the noise eliminating system can approach the power supply unit and the grounding unit as close as possible, thereby enhancing the performance of the passive component.
Another object of the present invention is to provide a noise eliminating system on chip and method of making the same to minimize the number of devices needed to be installed between the chip and the noise eliminating system, thereby decreasing accumulated impedance caused by high-frequency circuit between the chip and the noise eliminating system, thereby enhancing the performance of the passive component.
Still another object of the present invention is to provide a noise eliminating system on chip and method of making the same, in which the noise eliminating system is directly mounted on the upper surface of the chip, thereby saving a great deal of substrate space and making it possible to shrink the size of the printed circuit board or the substrate, and thus reduce the cost.
To achieve the above goals, a noise eliminating system on chip and method of fabricating the same are provided. A noise eliminating system is connected to a chip. There are guiding units provided on the chip for connecting with the noise eliminating system, thereby reducing simultaneous switching noise of the chip.
According to one aspect of this invention, a noise eliminating system on chip is provided. The noise eliminating system on chip comprises a chip; a power supply unit provided on the chip and being electrically connected to the chip; a grounding unit provided on the chip and being electrically connected to the chip; a guiding unit installed on an upper surface of the chip and being electrically connected to the power supply unit and the grounding unit; and at least one noise eliminating system comprising a connecting unit and a noise eliminating unit, wherein the connecting unit is electrically connected to the noise eliminating unit, and wherein the connecting unit is electrically connected to the guiding unit.
According to one aspect of this invention, a method for fabricating a noise eliminating system on chip, which comprises the steps of:
providing a chip having thereon a power supply unit and a grounding unit;
forming a guiding device layer on an upper surface of the chip;
etching the guiding device layer to form the guiding devices;
providing a noise eliminating system;
using surface mount technology to install the noise eliminating system on the upper surface of the chip, and the noise eliminating system connects to the guiding devices; and
jointing the junction between the noise eliminating system and the guiding devices such that the noise eliminating system is electrically connected to the guiding devices.
REFERENCES:
patent: 5808878 (1998-09-01), Saito et al.
patent: 5869894 (1999-02-01), Degani et al.
patent: 6181008 (2001-01-01), Avery et al.
patent: 6184585 (2001-02-01), Martinez et al.
patent: 6222246 (2001-04-01), Mak et al.
patent: 6222278 (2001-04-01), Muyamoto et al.
patent: 6424034 (2002-07-01), Ahn et al.
patent: 6489686 (2002-12-01), Farooq et al.
Clark Sheila V.
VIA Technologies Inc.
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