Noise and power optimization in high performance circuits

Details Noise and power optimization in high performance circuits Noise and power optimization in high performance circuits

2001-09-28

2004-04-13

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06721924

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to integrated circuit design. More particularly, the invention relates to a computer implemented method of modifying circuit characteristics that involves noise and power optimization.
2. Discussion
Integrated circuit (IC) design is a critical component to the development of personal computers (PCs), personal digital assistance (PDAs), wireless communication devices and many other systems. In order to achieve the desired functionality and speed, logic of varying complexity must often be developed for the IC. In the past, standard logic has been executed by complementary metal-oxide semiconductor (CMOS) circuitry, which is well documented and widely used in industry. More complex, high speed logic has used domino circuits, which include both dynamic and static gates. Domino circuitry is described in a number of sources as U.S. Pat. No. 6,275,071 to Ye et al.
It has been determined that a number of tradeoffs must be made when developing high speed circuits such as domino circuits. For example, power consumption is a particular parameter that is often at odds with timing constraints. As a general matter, in order to reduce delays, more robust, power consuming gates must be used. Other tradeoffs relate to noise reduction and real estate minimization.
Conventional approaches to modifying given circuit characteristics in accordance with the above-described tradeoffs involve determining a set of objective parameters such as available device sizes and power levels, and obtaining various constraints for the circuit. Typically, timing constraints and physical constraints are often used to provide practical limits on the reduction of power levels and real estate usage. Thus, signals must arrive “on time”, gates cannot be smaller than realistically possible, and the values of the objective parameters are optimized with these constraints in mind. While the above-described approach has been acceptable under certain circumstances, the increasing complexity of more recent logic architectures has brought to light a number of difficulties to be addressed.
A particular difficulty relates to noise. A major source of noise in an IC is capacitative and inductive coupling between two or more signal paths, and is often characterized as “crosstalk”. Although noise coupling can have profound effects on timing and power considerations, and can lead to functional failure in domino logic, conventional approaches to circuit optimization often do not take into account these effects.
Another concern with regard to IC design is the manner in which traditional technologies approach the actual optimization. For example, earlier designs worked with only one path at a time, rather than performing a simultaneous solution of tradeoffs in sizing across a multi-output block. It has been determined that such path-wise optimization methods can exhibit unreliable convergence even if margins and interaction with place-and-route is neglected. While certain attempts have been made at simultaneous optimization, the inability to consider noise constraints limits their practical usefulness. Furthermore, these approaches do not include a mechanism for employing realistic gate delay models, especially if these models are non-convex and discrete.
Additionally, reported methods do not describe a mechanism for leveraging the cost-function information from the results of an optimization step. Such a mechanism would enable re-synthesis of netlists in order to improve power versus delay optimization. Conventional methods also do not show wiring/shielding directives and power-cost sensitivities being used to facilitate convergence with logic synthesis and place-and-route operations. Furthermore, designer or project input templates cannot adequately be used to configure and control the optimization and synthesis processes. In addition, many conventional methods of modifying circuit characteristics do not demonstrate the ability to optimize a mix of fixed and continuously tunable gates.


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