Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-12-17
2001-08-28
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S204000, C711S137000, C711S169000
Reexamination Certificate
active
06282626
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is related to the field of processors, and more specifically to techniques for reducing memory access time in processing systems in order to improve performance.
In processing systems, it is typical to provide a processor coupled to a memory in which data used by the processor are stored. During the execution of a program, the processor accesses the memory in order to store or retrieve data. It is generally desirable that the memory have a sufficiently fast access time so that processing power is not wasted waiting for memory operations to complete. However, this goal must be balanced against other needs of the processing system. The memory also must be large enough to store sufficient data to minimize the performance impact of input/output (I/O) operations, which are extremely slow as measured in execution cycles of the processor. Also, the memory must generally be accessible to other entities, such as DMA controllers used to perform I/O operations. Memories that satisfy these other needs generally exhibit greater latency, or access time, than needed to achieve the best possible processing performance from a system.
There are known techniques for reducing the average access time of memory in a processing system. According to one technique, one or more read buffers having fast access time are placed near the processor, and are also coupled to the memory. When the processor makes a request for a word of data, a block of multiple words including the desired word is requested from memory. When the block is returned, the desired word is given to the processor, and the remainder of the block is stored in a read buffer. Subsequent processor requests for data words in the block are satisfied from the read buffer, and therefore are satisfied much more quickly than if additional requests to the system memory were required.
Although overall performance can thus be improved by using read buffers, there is still a performance limitation caused by the access time for data blocks. It would be desirable to further reduce average memory latency in order to achieve greater performance in processing systems.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a processing system is disclosed in which average memory latency can be further reduced below that of a system using read buffers alone.
In the disclosed processing system, the memory space accessible by the processor is partitioned such that multiple memory regions map to the same physical memory. Processor accesses in one of the regions are regarded as normal accesses, and are satisfied from the memory or a read buffer. If a memory access is required, the processor is stalled in a normal fashion until the desired data word is returned from the memory. Processor accesses to the other region are regarded as implied requests to prefetch the data from the memory and place it into a read buffer without stalling the processor. The processor is free to engage in useful activity while the data is being prefetched. At a later point in program execution, when the data is requested via the first region, the data likely resides in the read buffer, and thus can be provided to the processor very quickly. Thus, the processor is not required to wait while data is being obtained from the memory, so overall performance is improved.
Other aspects of the present invention will be apparent from the detailed description below.
REFERENCES:
patent: 5623636 (1997-04-01), Revilla et al.
patent: 5848254 (1998-12-01), Hagersten
patent: 5864692 (1999-01-01), Faraboschi et al.
patent: 5884027 (1999-03-01), Garbus et al.
patent: 5983306 (1999-11-01), Corrigan et al.
Chieffo Paul
Platko John J.
3Com Corporation
Portka Gary J.
Weingarten, Schurgin Gagnebin & Hayes LLP
Yoo Do Hyun
LandOfFree
No stall read access-method for hiding latency in processor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with No stall read access-method for hiding latency in processor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and No stall read access-method for hiding latency in processor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2443359