No-precharge FAMOS cell and latch circuit in a memory device

Details No-precharge FAMOS cell and latch circuit in a memory device No-precharge FAMOS cell and latch circuit in a memory device

2007-08-28

2007-08-28

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S096000

Reexamination Certificate

active

11472670

ABSTRACT:
The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission gate isolates the fuse from the latch. When a reset condition occurs, the data that was in latch circuit remains after the reset condition is complete.

REFERENCES:
patent: 5852580 (1998-12-01), Ha
patent: 5912841 (1999-06-01), Kim
patent: 5933370 (1999-08-01), Holzmann et al.
patent: 6021067 (2000-02-01), Ha
patent: 6426910 (2002-07-01), Santin
patent: 6590825 (2003-07-01), Tran et al.
patent: 6654272 (2003-11-01), Santin
patent: 6845029 (2005-01-01), Santin
patent: 2002/0122331 (2002-09-01), Santin
patent: 2004/0037131 (2004-02-01), Santin
patent: WO 02069347 (2002-09-01), None

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