NMOS transistor having inversion layer source/drain contacts

Details NMOS transistor having inversion layer source/drain contacts NMOS transistor having inversion layer source/drain contacts

1990-07-06

1991-09-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 17, 437 41, 437 44, 437984, 357 233, 357 239, H01L 21265

Patent

active

050473611

ABSTRACT:
A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).

REFERENCES:
patent: 3442721 (1969-05-01), McCaldin
patent: 3657614 (1972-04-01), Cricchi
patent: 3983574 (1976-09-01), Statz et al.
patent: 4047974 (1977-09-01), Harari

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