NMOS data storage cell for clocked shift register applications

Static information storage and retrieval – Systems using particular element – Flip-flop

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365189, 365203, 365233, 365 73, 3072721, G11C 700, G11C 1134, G11C 1140

Patent

active

048254096

ABSTRACT:
An improved NMOS storage cell for use in shift registers is disclosed. Among other components, it contains a pair of inverters--one them an enabling inverter. A pre-charge transistor is placed in parallel with the first inverter to decrease the rise time associated with the transition from a logic low level output to a logic high level output. The result of adding the pre-charge transistor to the circuit is to increase the speed of operation of the storage cell, without the accompanying decrease in density with prior art methods, where the components must be enlarged. Another aspect of the present invention which further increases the density of the cell is the elimination of the complement clock line found in many prior art storage cells. The previous combination of a second inverter and a pass transistor connected to a complement clock line, is replaced by an enabling inverter connected to the clock line.

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