NMOS circuit in isolated wells that are connected by a bias...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S158000, C257S277000, C257S278000, C257S276000, C257S544000, C257S233000

Reexamination Certificate

active

06630700

ABSTRACT:

FIELD OF THE INVENTIONS
The present inventions relate generally to integrated circuits, and more particularly to bias schemes for active device stacks on MOS integrated circuits having low supply voltages.
BACKGROUND OF THE INVENTIONS
Stacked devices are used commonly on analog and RF integrated circuits (ICs) in both single-ended and differential embodiments. As the operating voltages of integrated circuits decrease with succeeding generations of process technology, however, the stacked devices must be biased optimally to maintain the devices in saturation and maximize signal-handling ability. Particularly, for proper operation of N stacked devices plus a current source, the minimum supply voltage, V
DD
, must be N+1 times the gate-source voltage minus a threshold voltage plus a peak output signal swing, i.e., V
DD
>=(N+1)(V
GS
−V
T
)+V
S
, where V
GS
is the gate-source voltage, V
T
is the effective threshold voltage and V
S
is the peak output signal swing. The gate-source voltage, V
GS
, is typically 250 mV more than the effective threshold voltage, V
T
, which is about 400 mV. The NMOS threshold voltage, V
T
=V
TO
+g[sqrt(2Phi
F
+V
SB
)+sqrt(2Phi
F
)] (Equation 1), where V
TO
is the effective threshold voltage when the bulk and source are at the same potential, g is the bulk effect factor, Phi
F
is the absolute value of the Fermi potential, and V
SB
is the source-bulk voltage.
In a circuit having two stacked devices, for example, the supply voltage needs to be at least 0.75 V plus the peak signal swing, which is well within the maximum supply voltage of 1.8 V typical of present day ICs, but works only if the stacked devices are biased optimally.
A. R. Shahani et al. disclose a low threshold voltage process utilizing active common-mode feedback and resistor dividers to bias three stacked devices and a current source from a 1.5 V supply in “A 12-mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver”, IEEE Journal of Solid State Circuits, vol. 32, pp. 2061-2070, December 1997. The active common-mode feed back and resistor dividers of Shahani et al. however are relatively complex and require substantial area on the IC.
It is also known to bias a stack of circuit devices with a stack of diode-connected devices, which has the advantage of simplicity and small area on the IC. In the schematic diagram of Prior Art
FIG. 1
, the gate of each bias device M
1
-M
3
is coupled to the gate of the corresponding active device M
4
-M
6
, respectively, in a single-ended embodiment but could represent a simplification of a differential embodiment. In
FIG. 1
, the bodies of the diode-connected bias devices M
1
-M
3
and the bodies of the active devices M
4
-M
6
are coupled to ground. In
FIG. 1
, the gate-source voltage, V
GS
, increases at each level of the stack above the first level because the bulk of the devices are connected to ground. The circuit of
FIG. 1
is biased less than optimally and requires a relatively high supply voltage due to the body effect, which is characterized by a voltage between the source and bulk of each device. The body effect causes an increase in the effective threshold voltage, V
T
, according to Equation 1. In
FIG. 1
, the required minimum supply voltage V
DD
is the larger of (N+1)
VGS
for the bias stack or (N+1)V
GS
−V
T
′+V
S
for the active stack and is more than the typical available supply voltage of 1.8 V, where V
T
′ is V
T
+deltV and V
GS
, V
T
and V
S
are as defined above and deltV is the increase in threshold voltage caused by the body effect according to Equation 1.
The various aspects, features and advantages of the present invention will become more fully apparent to those having ordinary skill in the art upon careful consideration of the following Detailed Description of the Invention with the accompanying drawings described below.


REFERENCES:
patent: 6111282 (2000-08-01), Gonzalez
patent: 6388483 (2002-05-01), Mizuno et al.
patent: 6521946 (2003-02-01), Mosher
Arvin R. Shahani, Derek K. Shaeffer, and Thomas H. Lee, A 12-mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver, IEEE Journal of Solid-State Circuits, vol. 32, No. 12, Dec. 1997, pp. 2061-2070.
Ming-Jer Chen, Jih-Shin Ho, Tzuen-His Huang, Chuang-Hen Yang, Yeh-Ning Jou, and Terry Wu, Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Circuits, IEEE Transactions on Electron Devices, vol. 43, No. 6, Jun. 1996, pp. 904-910.
Torsten Lehmann and Marco Cassia, 1-V Power Supply CMOS Cascode Amplifier, IEEE Journal of Solid-State Circuits, vol. 36, No. 7, Jul. 2001, pp. 1082-1086.
Chi-Nan Brian Li, Didier Farenc, Rana Singh, Jane Yater, Sarah Liu, Chia-Lin Chang, Sandeep Bagchi, Kevin Chen, Paul Ingersoll and Kuo-Tung Chang, A Novel Uniform-Channel-Program-Erase (UCPE) Flash EEPROM Using An Isolated P-well Structure, IEDM Tech. Digest, No. 33.5.1-33.5.4, Apr. 2000, pp. 779-782.
PCT/US02/30340 PCT Search Report mailed Mar. 7, 2003.

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