NMOS charge-sharing prevention device for dynamic logic circuits

Details NMOS charge-sharing prevention device for dynamic logic circuits NMOS charge-sharing prevention device for dynamic logic circuits

1996-09-17

1998-11-17

Tokar, Michael J.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 95, 326106, H03K 19096, H03K 19084

Patent

active

058381694

ABSTRACT:
A logic block comprised of several transistors is provided. The logic block has several inputs and an output for communicating the result of its logic operation. A precharge device having a clock input is connected to the output of the logic block. The precharge device periodically allows the output of the logic block to become valid. This is accomplished by holding the output of the logic block at a fixed voltage level when the clock input is at a first voltage level, and when the clock input changes to a second voltage level, the precharge device allows the result of the logic function performed by the logic block to appear at the output of the logic block. Also, a charge redistribution prevention device is connected to at least one of the transistors included in the logic block. The charge redistribution prevention device prevents charge redistribution by applying a voltage to at least one of the transistors in the logic block. Applying a voltage in this manner equalizes the difference in voltage between internal nodes of the logic block and the output of the logic block, thereby preventing charge from redistributed.

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patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5065048 (1991-11-01), Asai et al.
patent: 5146115 (1992-09-01), Benhamida
patent: 5661675 (1997-08-01), Chin et al.

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