Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-11-10
1999-08-10
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257371, 257607, 257914, H01L 2976, H01L 2994, H01L 29167, H01L 29107
Patent
active
059362871
ABSTRACT:
An integrated circuit fabrication method incorporating nitrogen into the polysilicon-dielectric interface in an MOS transistor. A semiconductor substrate having a P-well region and an N-well region is provided. Each well region includes channel regions and source/drain regions. A dielectric layer, preferably a thermal oxide, is formed on an upper surface of the semiconductor substrate. The thermal oxide can be grown in a nitrogen bearing ambient, an O.sub.2 ambient, or an H.sub.2 O ambient. Alternatively, the dielectric may be formed from a deposited oxide. Thereafter, a layer of polysilicon is formed on the dielectric layer and a plurality of "nitrogenated" polysilicon gates is formed on the dielectric layer over the channel regions. In a presently preferred embodiment, nitrogen species are introduced into the polysilicon gates with an ion implantation step. The nitrogen implantation step may alternatively be performed before or after the patterning of the polysilicon layer. If implantation occurs after patterning of the polysilicon layer, nitrogen will be introduced into the source/drain regions and effect an increase in drive current without a corresponding increase in leakage current. In a presently preferred embodiment, a dose of between 5.times.10.sup.13 cm.sup.-2 and 1.times.10.sup.16 cm.sup.-2 is used for implanting the nitrogen bearing species and the species is distributed within the plurality of polysilicon gates such that the concentration of the nitrogen is greatest at approximately a midpoint within said gates. The semiconductor substrate may be subsequently annealed in an ambient maintained between approximately 900.degree. to 1100.degree. C. preferably using a rapid thermal anneal apparatus.
REFERENCES:
patent: 4774197 (1988-09-01), Haddad et al.
patent: 4897368 (1990-01-01), Kobushi et al.
patent: 4914046 (1990-04-01), Tobin et al.
patent: 5250456 (1993-10-01), Bryant
patent: 5266816 (1993-11-01), Seto et al.
patent: 5429972 (1995-07-01), Anjun et al.
patent: 5470764 (1995-11-01), Ikegami et al.
patent: 5516707 (1996-05-01), Loh et al.
patent: 5567638 (1996-10-01), Lin et al.
patent: 5581092 (1996-12-01), Takemura
patent: 5605848 (1997-02-01), Ngaoaram
patent: 5610084 (1997-03-01), Solo de Zaldivar
Kuroi et al., "Novel NICE (Nitrogen Implantation into CMOS Gate Electrode and Source-Drain) Structure for High Reliability and High Performance 0.25 .mu.m Dual Gate CMOS," IEDM Tech DIG. 1993, pp. 325-328.
Wolf et al., "Silicon Processing for the VLSI Era, vol. 1: Process Technology," Lattice Press 1986, pp. 168-171, 182-185, 198-200, 209-215, and 261-265.
Patent Abstracts of Japan, vol. 16, No. 447 (E-1266), Sep. 17, 1992 & JP 04 157766 A, May 29, 1992.
International Search Report for PCT/US 97/02514 dated Jul. 4, 1997.
Fulford Jr. H. Jim
Gardner Mark I.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Ngo Ngan V.
LandOfFree
Nitrogenated gate structure for improved transistor performance does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nitrogenated gate structure for improved transistor performance , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nitrogenated gate structure for improved transistor performance will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1122498