Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-05-06
2002-04-16
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S410000, C257S412000, C257S344000, C257S369000
Reexamination Certificate
active
06373113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an improved method for forming a transistor by incorporating nitrogen into the transistor gate and gate dielectric.
2. Description of the Relevant Art
The conventional fabrication of MOS (metal-oxide-semiconductor) transistors within a semiconductor substrate is well known. Typically, the substrate is divided into a plurality of active regions and isolation regions through an isolation process such as field oxidation or shallow trench isolation. After the isolation and active regions have been formed, the active regions may be further divided into n-well active regions and p-well active regions by implanting n-type dopants and p-type dopants into their respective wells. A thin oxide is then grown on an upper surface of the semiconductor substrate in the active regions. This thin oxide serves as the gate oxide for subsequently formed transistors. Thereafter, a plurality of polysilicon gate structures are formed wherein each polysilicon gate traverses an active region, effectively dividing the active region into a pair of source/drain regions disposed on either side of each gate structure and a channel region disposed below each gate structure. After formation of the polysilicon gates, a p-type source/drain implant is performed to introduce p-type impurities into the source/drain regions of the n-wells and an n-type source/drain implant is performed to introduce n-type impurities into the source/drain regions of the p-wells. The dopant species used in conventional transistor processing typically includes phosphorus and arsenic for n-type impurities and boron for p-type impurities.
As transistor geometries shrink below 0.5 micron, the limitations of conventional transistor processing become more and more apparent. As the thickness of the gate oxide decreases below 100 angstroms, devices become more susceptible to diffusion of impurities contained within the gate structure across the gate oxide and into the active area of the transistor. This problem is especially acute for gate structures into which boron is implanted (e.g., p+ polysilicon gates) because of the relatively high rate at which boron diffuses through silicon and silicon dioxide. In addition, it is believed that many loosely formed bonds exist at the interface between the gate oxide structure and the polysilicon gate structure in conventionally formed transistors. The presence of these loosely formed bonds is believed to contribute to undesirable transistor characteristics such as susceptibility to voltage breakdown. Still further, as devices become smaller and more densely packed upon a semiconductor substrate surface, it becomes increasingly important to minimize the leakage current of each individual transistor. It is believed that leakage current can be created by a scattering effect that occurs as electrons traverse the channel between a device's source region and drain region. As the number of transistor devices within a single integrated circuit increases, leakage current can become significant enough to raise the temperature of the semiconductor substrate, slowing the device and, eventually, raising the temperature above the operational limit of the device.
Therefore, it would be highly desirable to fabricate MOS transistors in a manner that reduces or eliminates diffusion from a gate structure to an underlying active region of the transistor; improves the bond structure of the polysilicon gate oxide interface, thereby improving the characteristics of the interface; and increases the source/drain drive current without a corresponding increase in leakage current.
SUMMARY OF THE INVENTION
The problems outlined above are in large part addressed by a method of fabricating an integrated circuit in which nitrogen is incorporated into the gate dielectric and transistor gate. The nitrogen in the silicon gate is believed to facilitate the formation of stronger bonds with the underlying dielectric, preferably an oxide, resulting in improved transistor characteristics including higher gate oxide breakdown voltages. The presence of nitrogen within the gate structure also inhibits the diffusion of impurities, particularly boron, from the gate structure into the active region of the underlying transistor. The reduction of dopant diffusion across the gate dielectric enables the formation of devices with thinner gate oxides and, therefore, superior operating characteristics.
Broadly speaking, the present invention contemplates a method of fabricating an integrated circuit. The method comprises the providing of a semiconductor substrate that has a p-well region and an n-well region. The n-well region is laterally displaced from the p-well region. The n-well and the p-well each include a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate includes a p-type epitaxial layer having a resistivity of approximately 10 to 15 &OHgr;-cm formed on a p+silicon bulk. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600 to 900° C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500 to 650° C. A nitrogen-bearing impurity distribution is then introduced into the conductive gate layer and the dielectric layer. The introduction of the nitrogen-bearing impurity distribution is suitably accomplished by implanting a nitrogen-bearing molecule such as N, N
2
, NO, NF
3
, N
2
O, or NH
3
. Ideally, a peak concentration of the nitrogen-bearing impurity distribution is in the range of approximately 1×10
15
to 1×10
19
atoms/cm
3
and is located proximal to an interface of the conductive gate layer and the dielectric layer. Thereafter, an anneal may be performed, preferably in a rapid thermal process, at a temperature of approximately 900 to 1100° C. for a duration of less than approximately 5 minutes. The conductive gate layer is patterned to form first and second conductive gate structures over the channel regions of the p-well and n-well respectively. Thereafter a first n-channel source/drain impurity distribution may be introduced into the source/drain regions of the p-well and a first p-channel source/drain impurity distribution may be introduced into the source/drain regions of the n-well.
The present invention further contemplates an integrated circuit. The integrated circuit includes a semiconductor substrate, preferably comprising silicon, having a p-well and a laterally displaced n-well. A dielectric layer is located on an upper surface of the semiconductor substrate. The dielectric layer includes an impurity distribution comprising a nitrogen-bearing molecule such as NO, NF
3
, N
2
O, or NH
3
. Preferably, the dielectric layer is a thermal oxide having a thickness of less than approximately 50 angstroms. The integrated circuit further includes a first and a second gate structure formed on the dielectric layer over respective channel regions in the n-well and p-well. Like the dielectric layer, the gate structures include a nitrogen bearing impurity distribution. The gate structures preferably comprise polysilicon having a sheet resistivity less than approximately 500 &OHgr;/square. A first source/drain impurity distribution is substantially contained within a first pair of source/drain regions laterally displaced on either side of the first channel region while a second source/drain impurity distribution is substantially contained within a second pair of source/drain regions laterally displaced on either side of the second channel region. The first source/drain impurity distr
Gardner Mark I.
Gilmer Mark C.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Loke Steven
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