Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-28
2003-11-18
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000, C257S314000
Reexamination Certificate
active
06649971
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a nitride read only memory (NROM) cell. More particularly, the present invention relates to a NROM cell for reducing the second-bit effect.
2. Description of Related Art
The fabrication of a NROM cell includes forming a trapping layer on a substrate. The trapping layer is formed by providing an oxide
itride/oxide (ONO) stacked layer structure with the silicon nitride layer serving as the trapping layer. The read only memory cell that uses this type of material as the electrons trapping layer is known as a nitride read only memory cell. A gate is further formed on the silicon oxide/silicon nitride/silicon oxide layer, followed by performing an ion implantation process on the substrate to form a source/drain region in the substrate adjacent to the gate structure.
For a nitride read only memory cell, a single NROM cell can store 1 bit each at the side of the source region and at the side of the drain region in the trapping layer. However, if one bit of data is already stored in the trapping layer at the side of the drain region, a second-bit effect is generated during the forward reading. In other words, the bit of information that is already stored in the trapping layer would affect the forward reading by raising the barrier substantially, resulting in an increase of the forward read threshold voltage. To resolve the aforementioned problems, increasing the drain voltage (V
d
) and therefore increasing the drain-induced barrier lowering (DIBL) effect is traditionally used. However, as the scaling-down of the device dimension continues, a high drain voltage would lead to operational difficulties.
SUMMARY OF INVENTION
Accordingly, the present invention provides a NROM cell and a fabrication method thereof, wherein the second-bit effect is lower to prevent the increase of the DIBL effect. The reverse read threshold voltage is thereby increased.
The present invention provides a NROM cell for reducing the second-bit effect and a fabrication method thereof, wherein the DIBL effect is mitigated while the forward read is maintained.
In accordance to the present invention, a NROM cell for reducing the second bit effect is provided. The NORM cell of the present invention comprises a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. Further, the depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow traveling to the source/drain regions.
The present invention provides a fabrication method for a nitride read-only memory cell for reducing the second-bit effect comprises forming a silicon oxide/silicon nitride/silicon oxide layer, followed by forming a gate on the silicon oxide/silicon nitride/silicon oxide layer. Thereafter, a shallow pocket ion implantation is performed on the substrate to form a shallow pocket doped region in the substrate beside the gate, wherein the depth of the shallow pocket doped region is sufficiently small to preclude interference to the forward read current flow. Ions are further implanted to the substrate at the peripheral of the shallow pocket doped region to form the source/drain regions.
The present invention provides a shallow doped region between the source/drain regions and the ONO layer beside the gate. Further, the depth of this shallow doped region is small enough to prevent interference to the forward read current flow. Therefore, an increase of the DIBL effect is prevented and the reverse read threshold voltage is increased. Further, since the depth of the pocket doped region is sufficiently small to prevent interference to the forward read current flow, the DIBL effect is mitigated while the forward read is maintained. Further, according to the present invention, the DIBL effect is attenuated without increasing the drain voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6168993 (2001-01-01), Foote et al.
patent: 6391730 (2002-05-01), Kluth et al.
patent: 6538270 (2003-03-01), Randolph et al.
patent: 2001/0048612 (2001-12-01), Yi et al.
Chan Kwang-Yang
Fan Tso-Hung
Liu Mu-Yi
Lu Tao-Cheng
Tsai Wen-Jer
Ho Hoai
Ho Tu-Tu
Jianq Chyun IP Office
Macronix International Co. Ltd.
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