Nitride etch stop for poisoned unlanded vias

Details Nitride etch stop for poisoned unlanded vias Nitride etch stop for poisoned unlanded vias

1998-09-28

2001-05-29

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S734000, C438S740000

Reexamination Certificate

active

06239026

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to methods for forming interconnect structures within integrated circuit devices. More particularly, the present invention relates to the reduction of poisoned vias in a submicron integrated circuit device by reducing the occurrence of over-etched vias through the inclusion of a nitride etch-stop layer.
BACKGROUND OF THE INVENTION
Many advancements in the semiconductor fabrication industry have enabled the production of smaller, faster, and more efficient integrated circuit devices. However, the reduction in integrated circuit device dimensions may be limited by various process parameters. For example, in 0.25 &mgr;pm and smaller process technology using low dielectric constant insulating material between metal conductors, circuit devices often fail as a result of high via resistance caused by poisoned, unlanded vias.
FIG. 1
illustrates the cross section of a portion of a semiconductor wafer
8
fabricated in accordance with techniques commonly used in the industry. Wafer
8
of
FIG. 1
includes a substrate layer
10
which is typically formed from silicon. An insulating layer
20
may be formed directly above substrate layer
10
. Conductive material
30
may be deposited onto insulating layer
20
and suitably etched into conductive lines or portions. A layer
40
of material having a low dielectric constant, i.e., a “low-k” material, is spun onto conductive layer
30
such that low-k layer
40
fills in gaps
41
located in between the conductive lines of conductive layer
30
, thus insulating the lines of conductive layer
30
from neighboring lines. After low-k layer
40
is cured, insulating layer
50
is then deposited on top of low-k layer
40
. Insulating layer
50
then undergoes chemical mechanical planarization (“CMP”) to smooth out insulating layer
50
. CMP processes are well known in the industry and inherently produce wide-ranging thicknesses of insulating layer
50
. The thickness of insulating layer
50
varies between wafers as well as within each wafer.
To create interconnects between conductive portions of wafer
8
, vias or holes
60
(
FIG. 1
showing one via) are etched through insulating layer
50
and low-k layer
40
to conductive layer
30
. Via
60
is targeted for the center of a conductive line of conductive layer
30
, but some tolerance is permitted for misalignment. A via that lands directly on a conductive line is called a landed via. A via that lands partly on a conductive line and partly off the conductive line is called an unlanded via. A conductive filler material such as tungsten may be deposited into via
60
to connect the conductive line of conductive layer
30
with another conductive element (not shown) formed above insulating layer
50
.
Because of the varying thickness of insulating layer
50
resulting from the CMP process, the depth of the etch required to reach the top of conductive layer
30
is uncertain. In the event of an over-etch, i.e., an etch that goes too deep into low-k layer
40
, an unlanded via may develop into a poisoned via
62
(as shown in FIG.
2
). More specifically, the additional etching causes via
62
to penetrate into low-k layer
40
beyond the upper surface of conductive layer
30
. This results in an increase in the surface area of via
62
defined by low-k layer
40
.
Low-k layer
40
absorbs moisture which will outgas into via
62
during the deposition of the filler material. This moisture will react with the filler material and prevent the optimized formation of the filler material inside via
62
. The amount of moisture being outgassed is directly proportional to the amount of surface area of low-k layer
40
forming via
62
. Thus, in the case of an over-etch of an unlanded via, a much larger surface area of low-k layer
40
forms via
62
, as compared to the case of an optimally etched landed via
60
as shown in
FIG. 1
, which increases the chances that the filler material will not properly form inside the via. The resulting connection between conductive layer
30
and the filler material will not be optimal and will exhibit a high via resistance.
If one via is poisoned the entire integrated circuit device may fail. Currently, the yield of 0.25 &mgr;m integrated circuit devices is low because of failures resulting from unlanded poisoned vias.
Previous attempts have been made to solve the problems of unlanded poisoned vias with the implantation of arsenic ions. After a low-k layer has been spun onto a wafer, arsenic ions are implanted into the low-k layer so that the low-k layer will not absorb moisture. This procedure prevents outgassing from occurring, enabling the filler material to properly fill inside the vias. However, there are several problems with this procedure. First, the implantation of the arsenic ions raises the dielectric constant of the low-k layer. In addition, the implantation requires the use of arsenic, a poisonous element, which causes many health-related problems. Moreover, the process requires an additional step of implanting the arsenic ions which greatly increases manufacturing costs.
In addition, a possible solution might be to measure each semiconductor wafer after the CMP process to determine the thickness of each wafer, and thus determine the depth of the etch that would be required to create the via. However, this process would be extremely costly in that it would be time consuming and labor intensive, resulting in a slow production line.
SUMMARY OF THE INVENTION
Accordingly, it is an advantage of the present invention to reduce the formation of poisoned vias on semiconductor wafers using submicron process technology by the addition of an etch-stop layer.
The above and other advantages are carried out in one form by a semiconductor device comprised of: a foundation layer, a conductive layer formed and etched above the foundation layer, a low dielectric constant layer which is formed above the conductive layer, an etch-stop layer which is formed above the low dielectric constant layer, an insulating layer which is formed above the etch-stop layer and at least one via etched through the insulating layer, the etch-stop layer and the low dielectric constant layer to the conductive layer. With respect to the conductive layer, the vias may be landed vias or unlanded vias, or a combination thereof.
The vias are preferably etched in a three-step process. The three-step etch process may include a first non-selective etch which may go through at least some portion of the insulating layer, a second selective etch which may go through some additional portion of the insulating layer, and a third non-selective etch which may go through the etch-stop layer and the low dielectric constant layer and which stops at the conductive layer.


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