Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-26
2003-01-21
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C257S506000
Reexamination Certificate
active
06509604
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to nonvolatile memory devices. Even more particularly, the present invention relates to flash memory utilizing periphery and core stacks.
BACKGROUND OF THE INVENTION
Memory devices such as flash memory or electrically erasable programmable read only memory (EEPROM) are known. Memory devices such as flash memory comprise, core stacks, which hold the erasable programmable data, and periphery stacks which are used to program the core stacks. Manufacturing periphery stacks and core stacks on the same chip is advantageous and is done in the related art. However, sometimes using local oxidation of silicon (LOCOS) on part of the flash memory and shallow trench isolation (STI) on other parts of the flash memory is desirable. For instance, where shallow trench isolation is used for the periphery stacks, corner recesses, which are detrimental to the periphery stacks, form around the shallow trench isolation. In addition, core stacks and periphery stacks require different manufacturing steps. Some of these different processing steps for the core stacks are harmful to the periphery stacks and vice versa. One example of these problems is related to the use of a nitrogen implant or other nitridation methods to improve the functionality of the tunnel oxide of the core stacks. In the related art, such a nitrogen implant tends to contaminate the gate oxide of the periphery stack, thereby diminishing the performance of the gate oxide. Manufacturing periphery stacks and core stacks on a single chip is desirable. Thus, minimizing damage to the periphery stacks and core stacks from the different processes required to manufacture the different stacks is also desirable. Also, having periphery stacks with gate oxides of different thicknesses is a desirable condition.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention involves the use of successive hard masks to provide STI and LOCOS isolation on a single chip and the fabrication of a flash memory device on a substrate by using a hard mask to protect the periphery before forming a NITRIDATED tunnel oxide. Advantages of the present invention include the capability of fabricating a plurality of semiconductor devices on a single chip, wherein some of the devices are separated by shallow trench isolation and other devices are separated by local oxidation of silicon, the capability of fabricating a flash memory with a reduced contamination of the gate oxide, and the capability of fabricating a flash memory device with improved stack isolation. Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION.”
REFERENCES:
patent: 5658812 (1997-08-01), Araki et al.
patent: 5712205 (1998-01-01), Park et al.
patent: 5858830 (1999-01-01), Yoo et al.
patent: 5972751 (1999-10-01), Ramsbey et al.
patent: 6004847 (1999-12-01), Clementi et al.
patent: 6004862 (1999-12-01), Kim et al.
patent: 0 751 560 (1995-06-01), None
patent: 07111288 (1995-04-01), None
Chang Chi
Pham Tuan Duc
Ramsbey Mark T.
Sun Yu
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Prenty Mark V.
LandOfFree
Nitridation barriers for nitridated tunnel oxide for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nitridation barriers for nitridated tunnel oxide for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nitridation barriers for nitridated tunnel oxide for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3033230