Next generation 8B10B architecture

Details Next generation 8B10B architecture Next generation 8B10B architecture

2007-02-27

2007-02-27

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

10977952

ABSTRACT:
Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

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patent: 6812870 (2004-11-01), Kryzak et al.
Altera Corporation, “8B10B Encoder/Decoder: MegaCore Function User Guide,” Megacore Version 1.4.0, Document Version 1.4.0 Rev. 1, Feb. 2004.

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