Network with programmable interconnect nodes adapted to...

Details Network with programmable interconnect nodes adapted to... Network with programmable interconnect nodes adapted to...

2007-01-02

2007-01-02

Tsai, Henry W. H. (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral configuration

C710S100000

Reexamination Certificate

active

10829646

ABSTRACT:
A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.

REFERENCES:
patent: 4539655 (1985-09-01), Trussell et al.
patent: 6584535 (2003-06-01), Ouellet et al.
patent: 2002/0107952 (2002-08-01), Mancusi et al.
patent: 2004/0210693 (2004-10-01), Zeitler et al.

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