Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-03-29
2011-03-29
Patel, Kaushikkumar (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C712S010000, C370S356000
Reexamination Certificate
active
07917703
ABSTRACT:
A network on chip (‘NOC’) comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block coupled to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
REFERENCES:
patent: 4813037 (1989-03-01), Debuysscher et al.
patent: 5761516 (1998-06-01), Rostoker et al.
patent: 5884060 (1999-03-01), Vegesna et al.
patent: 6085315 (2000-07-01), Fleck et al.
patent: 6145072 (2000-11-01), Shams et al.
patent: 6151668 (2000-11-01), Pechanek et al.
patent: 6567895 (2003-05-01), Scales
patent: 6668308 (2003-12-01), Barroso et al.
patent: 6725317 (2004-04-01), Bouchier et al.
patent: 6891828 (2005-05-01), Ngai
patent: 6950438 (2005-09-01), Owen et al.
patent: 7162560 (2007-01-01), Taylor et al.
patent: 7394288 (2008-07-01), Agarwal
patent: 7398374 (2008-07-01), DeLano
patent: 7464197 (2008-12-01), Ganapathy et al.
patent: 7493474 (2009-02-01), Pechanek et al.
patent: 7500060 (2009-03-01), Anderson et al.
patent: 7502378 (2009-03-01), Lajolo et al.
patent: 7521961 (2009-04-01), Anderson et al.
patent: 7546444 (2009-06-01), Wolrich et al.
patent: 7568064 (2009-07-01), Reblewski et al.
patent: 2002/0099833 (2002-07-01), Steely et al.
patent: 2002/0178337 (2002-11-01), Wilson et al.
patent: 2003/0065890 (2003-04-01), Lyon
patent: 2004/0088487 (2004-05-01), Barroso et al.
patent: 2004/0260906 (2004-12-01), Landin et al.
patent: 2005/0166205 (2005-07-01), Oskin et al.
patent: 2005/0238035 (2005-10-01), Riley
patent: 2006/0209846 (2006-09-01), Clermidy et al.
patent: 2007/0055826 (2007-03-01), Morton et al.
patent: 2007/0076739 (2007-04-01), Manjeshwar et al.
patent: 2008/0134191 (2008-06-01), Warrier et al.
patent: 2008/0186998 (2008-08-01), Rijpkerna
patent: 2009/0083263 (2009-03-01), Felch et al.
patent: 2009/0282222 (2009-11-01), Hoover et al.
“The Power of Priority: NoC based Distributed Cache Coherency” by Bolotin et al., published May 21, 2007 by IEEE, ISBN: 0-7695-2773-6/07, pp. 117-126).
“A Network on Chip Architecture and Design Methodology” by Kumar et al. Published 2002, ISBN 0-7695-1486-3/02 by IEEE, pp. 8.
Office Action Dated Jan. 29, 2010 in U.S. Appl. No. 11/945,396.
Final Office Action Dated Jan. 15, 2010 in U.S. Appl. No. 12/031,733.
U.S. Appl. No. 12/117,897, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/031,733, filed Feb. 15, 2008, Hoover, et al.
U.S. Appl. No. 12/108,846, filed Apr. 24, 2008, Kuesel, et al.
U.S. Appl. No. 12/108,770, filed Apr. 24, 2008, Mejdrich et al.
U.S. Appl. No. 12/029,647, filed Feb. 12, 2008, Hoover et al.
U.S. Appl. No. 12/118,017, filed May 9, 2008, Comparan, et al.
U.S. Appl. No. 12/118,059, filed May 9, 2008, Mejdrich, et al.
U.S. Appl. No. 12/117,875, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/121,222, filed May 15, 2008, Kriegel, et al.
U.S. Appl. No. 11/936,873, filed Nov. 8, 2007, Hoover, et al.
U.S. Appl. No. 12/134,364, filed Jun. 9, 2008, Hoover, et al.
U.S. Appl. No. 11/937,579, filed Nov. 9, 2007, Mejdrich, et al.
U.S. Appl. No. 12/102,033, filed Apr. 14, 2008, Heil, et al.
U.S. Appl. No. 12/118,272, filed May 9, 2008, Kuesel, et al.
U.S. Appl. No. 12/118,039, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 11/945,396, filed Nov. 27, 2007, Hoover, et al.
U.S. Appl. No. 12/015,975, filed Jan. 17, 2008, Comparan, et al.
U.S. Appl. No. 12/117,906, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/233,180, filed Sep. 18, 2008, Hoover, et al.
U.S. Appl. No. 12/113,286, filed May 1, 2008, Heil, et al.
U.S. Appl. No. 11/955,553, filed Dec. 13, 2007, Comparan, et al.
U.S. Appl. No. 12/031,738, filed Feb. 15, 2008, Hoover, et al.
U.S. Appl. No. 11/972,753, filed Jan. 11, 2008, Mejdrich, et al.
U.S. Appl. No. 12/060,559, filed Apr. 1, 2008, Comparan, et al.
U.S. Appl. No. 11/926,212, filed Oct. 29, 2007, Hoover, et al.
U.S. Appl. No. 12/118,298, filed May 9, 2008, Heil, et al.
U.S. Appl. No. 12/118,315, filed May 9, 2008, Mejdrich, et al.
U.S. Appl. No. 11/938,376, filed Nov. 12, 2007, Mejdrich, et al.
U.S. Appl. No. 12/121,168, filed May 15, 2008, Hoover, et al.
Office Action Dated Jul. 20, 2009 in U.S. Appl. No. 12/031,733.
Kuskin, et al.; The Stanford Flash Multiprocessor; Jun. 6, 1996; Stanford University.
David Taylor, et al. “System on Chip Packet Processor for an Experimental Network Service Platform”. 2003.
Office Action Dated Mar. 30, 2010 in U.S. Appl. No. 11/926,212.
Final Office Action Dated May 19, 2010 in U.S. Appl. No. 11/945,396.
Intel, E8870 Chipset, Intel, Jun. 2002, pp. 1-10.
Office Action Dated Apr. 2, 2010 in U.S. Appl. No. 11/955,553.
Office Action Dated Mar. 24, 2010 in U.S. Appl. No. 12/031,733.
Walter, et al., “BENoC: A Bus-Enhanced Network on-Chip”. Dec. 2007, Technion, Israel Institute of Technology, Haifa, Israel.
Office Action Dated Jun. 8, 2010 in U.S. Appl. No. 12/118,298.
Office Action Dated May 26, 2010 in U.S. Appl. No. 12/117,875.
Comparan Miguel
Hoover Russell D.
Kuesel Jamie R.
Mejdrich Eric O.
Watson, III Alfred T.
Biggers & Ohanian LLP
International Business Machines - Corporation
Patel Kaushikkumar
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