Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1998-09-10
2001-08-21
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S005000, C710S065000, C710S120000
Reexamination Certificate
active
06279044
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to network interfacing and more particularly to a network interface for efficiently supplying data from a buffer memory to a host bus.
2. Background Art
Network interface devices are commonly used to transmit data between a host computer and network communication systems, such as a local area network. Typical network interface devices include Ethernet-type and IEEE 802.3. One of the primary functions of a network interface is to control the transfer of data between a buffer and the host bus. The data stored in the buffer is retrieved as a result of one of two types of requests, namely master and slave.
In master mode, a transfer is initiated by a master device which must arbitrate for use of the host bus with a host CPU prior to retrieving the data. In slave mode, the host CPU provides a target device with sufficient information to access the buffer and retrieve the data. A slave access can be performed using two different types of mapping, namely memory mapping and Input/Output (I/O) mapping.
Transmission of data from the buffer memory to the host bus has traditionally been accomplished by providing specific logic for each type of request.
FIG. 9
is a block diagram illustrating a typical buffer architecture
200
for accessing data from buffer memory. An interface unit
202
receives master and slave requests to access the buffer memory
204
. The request is directed to a transfer logic
206
that transfers data to or from the buffer memory
204
. The transfer logic
206
must be capable of handling each type of request individually. Thus, the interface unit
202
transfers the request to a specific logic portion in the transfer logic
206
based on the nature of the request. For example, the transfer logic
206
includes a first logic circuit
208
that services a master request, a second logic circuit
210
that services an I/O mapped slave request, and a third logic circuit
212
that services memory mapped slave requests.
Hence, a primary disadvantage associated with current methods of transferring data is the excessive amount of logic necessary to service the different types of requests. Another disadvantage is the increased latency encountered during the data transfer process. This latency can be defined as the delay between the time when data is retrieved from the buffer to the time it is delivered to the host bus. As previously mentioned, additional delays are encountered during transfers initiated by a master device, because the master device must arbitrate for access to the bus with other master devices that also require use of the bus.
DISCLOSURE OF THE INVENTION
There is a need for an arrangement for supplying data frames to a host bus that minimizes the logic necessary to access a buffer memory using different types of requests.
There is also a need for an arrangement for supplying data frames to a host bus that minimizes the latency encountered during the transfer of data from a buffer memory.
There is also a need for an arrangement for supplying data frames to a host bus that is capable of maintaining appropriate byte alignment regardless of the type of transfer.
These and other needs are attained by the present invention, where master and slave accesses to the buffer are serviced by a single logic circuit that eliminates the need for arbitration, reduces the amount of latency encountered during the data transfer process, and maintains appropriate byte alignment.
In accordance with one aspect of the present invention, a network interface for supplying data frames to a host bus comprises a buffer memory for storing a data frame received from a network according to a first byte alignment. A memory management unit is configured to transfer the stored data frame from the buffer memory in response to the one transfer request. The memory management unit includes request logic for generating a generic request to access the buffer memory in response to the one transfer request. A bus interface unit is configured for outputting the data frame onto a host bus according to a second byte alignment based on one of a master transfer request and a slave transfer request. The bus interface unit also includes a byte packing circuit configured for changing the first byte alignment of a portion of the stored data frame to the second byte alignment, prior to transfer to the host bus, based on the generic request. The generic request is serviced by a single logic circuit, eliminating the need for specialized logic to individually service master and slave requests. Hence, the network interface can perform master transfers or slave transfers with minimal logic. In addition, the byte packing circuit maintains the appropriate byte alignment regardless of the type of transfer.
Another aspect of the invention provides a method for accessing a buffer memory in a network interface. The method comprises generating a generic request in response to the detection of one of a master transfer request and a slave transfer request, reading a data frame from the buffer memory based on the generic request, determining a byte alignment for transmission of the data frame onto a host bus based on the generic request, and shifting bytes of the data frame for transfer onto the host bus based on the determined byte alignment. Generating a generic request enables a single logic circuit to service master and slave requests (both I/O and memory mapped) to access the buffer memory. Hence, a data frame from a buffer memory can be transferred to a host bus in accordance with a prescribed byte alignment for different transfer requests using minimal logic.
Additional objects, advantages, and novel features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumalities and combinations particularly pointed out in the appended claims.
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“High Speed Design for Dynamically Aligning Data in a Multi Byte Bus System” IBM Technical Disclosure Bulletin, Sep. 1994, vol. 37 No. 9, pp. 665-670.
Kuo Jerry Chun-Jen
Niu Autumn Jane
Advanced Micro Devices , Inc.
Cao Chun
Lee Thomas
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