Netlist redundancy detection and global simplification

Details Netlist redundancy detection and global simplification Netlist redundancy detection and global simplification

2005-01-25

2005-01-25

Do, Thuand (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C326S035000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06848094

ABSTRACT:
A method of global simplification of a netlist for an integrated circuit includes steps for generating a variable set representative of the inputs and outputs of logic elements in the netlist, re-ordering the inputs and corresponding outputs of the logic elements in the variable set, generating a key set representative of the inputs of the logic elements that are connected to the outputs, assigning names in the variable set that are representative of equivalent outputs having two or fewer essential variables to the same variable name, inserting names in the variable set representative of outputs having more than two essential variables, and assigning a value to each of the outputs having two or fewer essential variables.

REFERENCES:
patent: 5828228 (1998-10-01), Fant et al.
patent: 6333640 (2001-12-01), Fant et al.

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