Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-13
2009-10-06
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07600205
ABSTRACT:
The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with priority in order to improve a delay. To enable efficient elimination of a critical path, the method is arranged to include a wiring capacitance lower limit computation step for computing wiring capacitance lower limits on the basis of layout information; an inter-wiring capacitance computation step for computing, as an inter-wiring capacitance, a difference between a real wiring capacitance and the wiring capacitance lower limit; a parallel wiring length extraction step for extracting a parallel wiring length existing between adjacent wirings of the respective wirings; and a selection step for selecting a net/wiring whose layout is to be changed, on the basis of the inter-wiring capacitance, the parallel wiring length, and a slack value.
REFERENCES:
patent: 5892685 (1999-04-01), Sugiyama et al.
patent: 6110222 (2000-08-01), Minami et al.
patent: 6530066 (2003-03-01), Ito et al.
patent: 7191420 (2007-03-01), Ikeda
patent: 2003/0217344 (2003-11-01), Ito et al.
patent: 2004/0216067 (2004-10-01), Tanaka et al.
patent: 2007/0143723 (2007-06-01), Kawakami
patent: 7-93386 (1995-04-01), None
patent: 7-263559 (1995-10-01), None
patent: 10-313058 (1998-11-01), None
patent: 2000-357744 (2000-12-01), None
patent: 2001-93982 (2001-04-01), None
patent: 2002-280454 (2002-09-01), None
patent: 2002-313921 (2002-10-01), None
patent: 2003-58594 (2003-02-01), None
patent: WO 2004/046975 (2004-06-01), None
Japanese Office Notice of Grounds of Rejection mailed Oct. 28, 2008 for corresponding Japanese Patent Application No. 2004-168969.
U.S. Appl. No. 11/637,731, filed Dec. 13, 2006, Hiroshi Ikeda, Fujitsu Limited.
Dinh Paul
Fujitsu Limited
Staas & Halsey , LLP
LandOfFree
Net/wiring selection method, net selection method, wiring... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Net/wiring selection method, net selection method, wiring..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Net/wiring selection method, net selection method, wiring... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4142137