Net segment analyzer for chip CAD layout

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000

Reexamination Certificate

active

06817004

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to computer aided design (CAD) of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method of determining the physical characteristics of a selected net in a CAD layout of an integrated circuit chip design.
2. Description of the Prior Art
A typical CAD layout for an integrated circuit chip design typically includes a large number of nets. Each net connects an output of a device, such as a logic gate or a transistor, to the inputs of one or more devices in the net that constitute the integrated circuit. In analyzing a net from the CAD layout, it is often useful to see how the net is structurally connected to the devices connected to the net. A visual inspection of the net structure may assist the user in interpreting voltage contrast images, in analyzing failure mechanisms, in determining where to make circuit modifications, and in understanding the design layout. Previous methods for visually inspecting nets in an integrated circuit design include manipulating the CAD layout by changing the field of view, zooming, panning, and making various layers of the circuit design visible and hidden to trace the net routing manually. Such methods are generally time consuming and error prone.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method of displaying a net in a CAD layout for an integrated circuit chip includes steps for receiving a netlist of an integrated circuit design, displaying a CAD layout of the netlist, selecting a net segment in the CAD layout, and displaying a physical characteristics list of information items representative of physical characteristics of the net segment.
In another aspect of the present invention, a computer program product for displaying a net in a CAD layout for an integrated circuit chip includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform the following functions: displaying a CAD layout of an integrated circuit chip, selecting a net segment in the CAD layout, and displaying a physical characteristics list of information items representative of physical characteristics of the net segment.


REFERENCES:
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patent: 5367308 (1994-11-01), Weber
patent: 5392222 (1995-02-01), Noble
patent: 5895462 (1999-04-01), Toki
patent: 5937190 (1999-08-01), Gregory et al.
“Schematic Capture. Start Your Design”; Schematic Capture; Protel 99 SE; Dec. 16, 1999; pp. 1-7.
“Eliminate Guesswork With Board Signal”; Signal Integrity; Protel 99 SE; Dec. 16, 1999; pp. 21-23.
“Versatile Schematic or CUPL-based”; Programmable Logic Design; Protel 99 SE; Dec. 16, 1999; pp. 25-27.

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