Net delay optimization with ramptime violation removal

Details Net delay optimization with ramptime violation removal Net delay optimization with ramptime violation removal

2001-05-15

2003-01-14

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06507939

ABSTRACT:

FIELD
The invention relates to the field of integrated circuit design, and in particular to a method and system for timing optimization during integrated circuit design.
BACKGROUND
Integrated circuits consist of a large number of electronic components which include individual logic devices or groups of logic devices which are applied to the surface of a substrate, typically a silicon wafer. The components or “cells” are typically grouped to produce an application specific integrated circuit. For each application specific integrated circuit, placement of the components in optimum positions provides efficient layout of the components on the chip in order to reduce chip costs, processor delays, size and the like. Because the application specific integrated circuits typically contain hundreds of thousands if not millions of components, the task of optimizing the placement of components on a chip surface is not practical without the aid of computers.
In addition to the physical placement of cells on the chip, designers must also address timing issues associated with the propagation of signals from one cell to another. For this purpose the sequence of logic gates or other components in a net may be thought of as forming a “logic tree,” or more simply a “tree.” In order for the integrated circuit design to function properly the numerous signals being transmitted between cells in the tree must be substantially synchronized. Thus, designers must make allowance for the delays inherent in the components of the integrated circuit and the routing between the components. This may include inserting extra delays along certain faster routes, such as by addition of buffer components to synchronize those faster routes with slower routes.
However, while extra delays may be added, it desirable to minimize the total delays within a net and in particular to insure that no delay exceeds a specified maximum, a condition referred to as a “ramp time violation.” As integrated circuit designs continue to evolve to include more components and to operate at higher speeds, there is an accompanying continuing need for quicker, yet accurate, methods of analyzing and optimizing delays in a net.
SUMMARY
To address the aforementioned need, the present invention provides a method for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves. The steps of the method include inserting a plurality of auxiliary nodes into the tree so that no node is a greater distance removed from a next node than a predetermined value, defining discrete, approximate scales for delay, load, and ramp time, constructing, from a library set of buffers, a set of buffers chains for later insertion into the net tree, determining for each node on the tree a tradeoff function relating ramp time, departure time and load at the node, for each node, removing combinations of the tradeoff functions and the buffer chains, which when inserted into the tradeoff function, lead to a ramp time which exceeds a predetermined maximum allowable ramp time, for each node, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.
In certain preferred embodiments of the method the minimum delays are calculated in order from the leaves of the tree to its root and the buffer chains are thereafter inserted in reverse order from the root to the leaves.
In certain other preferred embodiments at least one of the approximate scales is a logarithmic scale. Moreover, both the ramp time and load scales are approximate.
It is also preferred that the buffer chains include combinations of inverting and noninverting buffers.
In still another preferred embodiment, the tradeoff function for each node is a monotonically decreasing step function. In another preferred embodiment, the tradeoff function is a vector function.
In another aspect, the invention relates to a program on a readable computer storage medium including instructions for performing the aforementioned method for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves.
In still another aspect, the invention relates to a computing device configured to perform a method for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves.


REFERENCES:
patent: 5774371 (1998-06-01), Kawakami
patent: 5917729 (1999-06-01), Naganuma et al.
patent: 6145117 (2000-11-01), Eng
patent: 6223334 (2001-04-01), Suaris et al.
patent: 6425115 (2002-07-01), Risler et al.

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