Nested loop method of identifying synchronous memories

Details Nested loop method of identifying synchronous memories Nested loop method of identifying synchronous memories

1997-07-16

1998-09-22

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Testing

365233, 36523003, 371 211, G11C 700

Patent

active

058124721

ABSTRACT:
A nested loop method for use in a memory test system to identify the width, depth, control line configuration, and part type of a synchronous memory, wherein bit patterns are retrieved from tables representative of a plurality of synchronous memories during execution of nested loops, from outer loop to inner loop, in the order of bank loop, RE loop, CE loop, CS loop, DQMB loop, and part type loop, and bits of an entry of a table occurring after a given entry are either a member of a superset or do not intersect bits of previous entries, and bits of an entry preceding the given entry are either a member of a subset or do not intersect bits of the given entry.

REFERENCES:
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5539692 (1996-07-01), Kajigaya et al.
patent: 5587950 (1996-12-01), Sawada et al.

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