Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Reexamination Certificate
2001-07-09
2003-04-08
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Accelerating charge or discharge
C365S230060, C365S228000, C365S227000, C365S226000
Reexamination Certificate
active
06545923
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to word line driver circuits for semiconductor memory devices.
2. Description of the Related Art
FIG. 1
illustrates a memory cell in a typical DRAM memory device. The refresh time of this memory cell is degraded by two major types of leakage current: I
1
which is the junction leakage current caused by defects at the junction boundary of transistor M
1
; and I
2
which is the channel leakage caused by sub-threshold current flowing through transistor M
1
. The junction leakage current I
1
can be reduced by decreasing the channel implantation dose, but this causes I
2
to increase. Similarly, the sub-threshold current I
2
can be reduced by increasing the threshold voltage Vth of M
1
, but this causes I
1
to increase.
A negatively biased word line scheme has been devised to reduce both the junction leakage current and the channel leakage current in the same time. A memory device employing a negative word line scheme applies a negative voltage Vbb (typically −0.4 to −0.5 Volts) to the word lines of non-selected memory cells. The implementation of negatively biased word line schemes, however, present numerous problems. First, a large negative voltage source is required to handle the high discharge currents that are generated when a word line is discharge from Vpp or Vdd to Vbb during a precharge operation. These discharge currents also tend to cause voltage fluctuations in Vbb. The current required to operate the word line control circuitry places additional demands on the negative voltage source. Thus, the negative voltage source tends to take up a large amount of space in a memory device. Second, conventional negative word line schemes require complex implementations that typically carry a chip area penalty because one negative word line driver is required per word line. Moreover, it is difficult to implement a negative voltage converter within a word line driver pitch.
SUMMARY
A negative word line drive scheme in accordance with the present invention diverts word line discharge current away from the negative voltage source during a precharge operation.
One aspect of the present invention is a method for discharging a word line comprising: coupling the word line to a first power supply; and diverting current from the word line to a second power supply.
Another aspect of the present invention is a semiconductor memory device comprising: a word line; and a word line driver circuit coupled to the word line and adapted to couple the word line to a first power supply during a precharge operation; wherein the word line driver circuit is adapted to divert word line discharge current to a second power supply during the precharge operation.
A further aspect of the present invention is a semiconductor memory device comprising: a word line; means for coupling the word line to a first power supply during a precharge operation; and means for diverting current from the word line to a second power supply during the precharge operation.
These and other aspects of the present invention are disclosed and claimed.
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patent: 2000-0045870 (2000-07-01), None
Sim Jae-Yoon
Yoo Jei-Hwan
Marger Johnoson & McCollom, P.C.
Tran Andrew Q.
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