Negative word line voltage regulation circuit for electrically e

Static information storage and retrieval – Floating gate – Particular biasing

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36518523, 36518529, 36518909, G11C 1604

Patent

active

059205059

ABSTRACT:
A negative word line voltage regulation circuit integratable in an electrically erasable semiconductor memory device. The circuit regulates a negative word line voltage to be supplied to word lines of the memory device during an electrical erasure of the memory device. The circuit includes an operational amplifier with a first input coupled to a reference voltage, a second input coupled to the negative word line voltage, and an output controlling a voltage regulation branch connected between an external power supply and the negative word line voltage, to provide a regulation current for regulating the negative word line voltage. The output of the operational amplifier also controls a voltage sensing branch, connected between the external power supply and the negative word line voltage, to provide a sensing signal coupled to the second input of the operational amplifier.

REFERENCES:
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5282170 (1994-01-01), Van Buskirk et al.
patent: 5392253 (1995-02-01), Atsumi et al.
patent: 5446697 (1995-08-01), Yoo et al.
patent: 5499212 (1996-03-01), Amanai
patent: 5600592 (1997-02-01), Atsumi et al.

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