Negative voltage level shift circuit

Details Negative voltage level shift circuit Negative voltage level shift circuit

1997-01-03

1997-12-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365226, G11C 1300

Patent

active

056967284

ABSTRACT:
A negative voltage level translator includes an output terminal which is electrically connected to a word line of the associated memory array. The voltage level of the output terminal, and thus the voltage level of the associated word line, is controlled by a cross-coupled latch. If the word line associated with the negative voltage level translator has been selected during erasing, the cross-coupled latch enters a first state which results in the output terminal being pulled to a negative erase voltage. This negative erase voltage, which may be generated by a negative charge pump, is in this manner coupled to the control gates of the array's selected memory cells to cause the erasing of such memory cells via, for instance, electron tunneling. If the word line associated with the output terminal has not been selected for erasing, the cross-coupled latch enters a second state which results in the output terminal being maintained at a floating potential. This floating potential is coupled to the control gates of un-selected memory cells and thereby precludes the erasing of such un-selected memory cells.

REFERENCES:
patent: 5193073 (1993-03-01), Bhuua

Affiliated with

Also associated with

Rating

Negative voltage level shift circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Negative voltage level shift circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Negative voltage level shift circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1613220