Negative voltage generating circuit

Details Negative voltage generating circuit Negative voltage generating circuit

2003-01-03

2004-03-16

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189090, C365S226000

Reexamination Certificate

active

06707703

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-003025, filed on Jan. 10, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a negative voltage generating circuit, and particularly to the circuit that generates a deeper negative voltage than −VDD, where VDD is a power supply voltage, and is suitable for use in a ferroelectric memory circuit.
2. Description of the Related Art
FIG. 7
is a view showing a prior art negative voltage generating circuit
1
(Document I: TECHNICAL REPORT OF IEICE, ICD2001-68 (2001-08); Document II: 2001 Symposium on VLSI circuit, C12-3).
FIG. 8
are voltage waveform diagrams showing the operation of the circuit of FIG.
7
.
A control circuit
2
generates control signals S
1
and S
2
as shown in
FIG. 8
to allow the output node N
0
to have negative voltage. This operation is described as follows.
Initially, the control signal S
1
, the voltage of the output node N
0
are at 0V, and the control signal S
2
is at a power supply voltage VDD, and thereby PMOS transistor switches SW
1
and SW
3
are off and a NMOS transistor switch SW
2
is on.
(t1) The control signal S
2
falls to 0V, so as to turn the NMOS transistor switch SW
2
off, and turn the PMOS transistor switch SW
3
on, thereby raising the voltage of a node N
1
to the power supply voltage VDD.
(t2) The control signal S
1
falls to −1V to turn the PMOS transistor switch SW
1
on.
(t3) The control signal S
1
rises to 0V, so as to turn the PMOS transistor switch SW
1
off, and bring the output node N
0
into a floating state.
(t4) The control signal S
2
rises to the power supply voltage VDD, so as to turn the PMOS transistor switch SW
3
off, and turn the NMOS transistor switch SW
2
on, thereby lowering the voltage of the node N
1
to 0V. Ideally, by the lowering of the voltage of the node N
1
, the voltage of the output node N
0
is lowered to −VDD. However, mainly due to the wire capacitance of the output node N
0
, it actually becomes −(VDD−&agr;), where &agr;>0.
In another negative voltage generating circuit using a charge pump, the output reaches a predetermined negative value by performing repeated operations, therefore the operation takes a long time and the power consumption becomes higher. In still another negative voltage generating circuit using a switched capacitor, its implementation is difficult since a forward direction current flows through PN junction in off state even when forming a switching transistor using twin well technology. In order to resolve this problem, the circuit must be complicated.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a negative voltage generating circuit that can generate a deeper negative voltage with simple constitution.
In one aspect of the present invention, there is provided a negative voltage generating circuit comprising: a first capacitor having first and second electrodes facing each other, the first electrode being connected to an output node; a first switching element connected between the output node and a first power supply voltage; a first switching circuit having an output connected through a first node to the second electrode, the first switching circuit selectively coupling the output to one of the first power supply voltage and a second power supply voltage higher than the first power supply voltage, or putting the output into a high impedance state; a second capacitor having first and second electrodes facing each other, the first electrode being connected to the first node; a second switching circuit having an output connected through a second node to the second electrode of the second capacitor, the second switching circuit selectively coupling the output thereof to one of the first power supply voltage and a third power supply voltage higher than the first power supply voltage, or putting the output thereof into a high impedance state.
A control circuit controls the first switching element, the first switching circuit, and the second switching circuit so that:
(1) in a first step, the first switching element is turned on, and the outputs of the first and second switching circuits are coupled to the second power supply voltage and the first power supply voltage, respectively;
(2) in a second step, the output of the second switching circuit is coupled to the third power supply voltage with the output of the first switching circuit being put in the high impedance state; and
(3) in a third step, the output of the first switching circuit is coupled to the first power supply voltage with the first switching element being off and the output of the second switching circuit being put in the high impedance state.
According to this configuration, the first and second capacitors (C
1
and C
2
) are brought into states as shown in FIGS.
3
(A) to
3
(C) by operations of the first to third steps, respectively, and therefore it is possible to generate a negative voltage deeper than −VDD, when the power supply voltage is VDD, with a simple structure.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 4964082 (1990-10-01), Sato et al.
patent: 5740109 (1998-04-01), Morton et al.
patent: 5892706 (1999-04-01), Shimizu et al.
patent: 2002-133857 (2002-05-01), None
“A Bit-Line GND Sense Technique for Low-Voltage Operation FeRAM,” Shoichiro Kawashima et al., 2001 Symposium on VLSI Circuit, C12-3.

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