Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-04
2007-12-04
Whitmore, Stacy (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11129785
ABSTRACT:
More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one. The NSRF value is calculated as equaling (ZWLM slack value+negative slack value)/ZWLM slack value=(1+(negative slack value/ZWLM slack value)), where ZWLM is a Zero Wire Load Model (ZWLM) value of timing wherein all wire parasitics are removed from consideration in the timing.
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Curtin James J.
McIlvain Kevin M.
Raphy Ray
Search Douglas S.
Szulewski Stephen
Augspurger Lynn L.
Dimyan Magid Y.
Whitmore Stacy
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