Static information storage and retrieval – Systems using particular element – Negative resistance
Reexamination Certificate
2000-12-22
2001-10-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Negative resistance
C365S175000, C365S177000, C365S071000
Reexamination Certificate
active
06310799
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to electronic circuit memories.
PRIOR ART DISCUSSION
At present, the two primary volatile memory technologies in use are Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM).
Dynamic Random Access Memory (DRAM) is a volatile random-access memory that stores information as a charge on a capacitor. This capacitor leaks charge with time and hence the memory needs to be periodically refreshed by the peripheral circuitry to retain its memory content. DRAM memories cannot match the speed of the central processor unit (CPU) due to charging current limits (during memory read/write operations) and destructive reading which necessitates rewrite operation. However, DRAM is the least expensive semiconductor memory available on the market today and hence is used in most computers as the core memory. DRAM cells consist of one transistor and one capacitor.
Static Random Access Memory (SRAM) is as fast as the CPU and is capable of storing a memory state as long as power is supplied to the computer. However, this added functionality is area-intensive because SRAM memory cells consist of either four or six CMOS transistors. SRAM memories are used as high-speed cache memories in computers.
There is therefore a requirement for a memory technology which has the advantages of SRAM, but is simpler and less expensive.
One prior approach to providing such a memory involves use of such negative resistance characteristics, and U.S. Patent No. U.S. Pat. No. 3,974,486 describes a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) which exhibits two-terminal negative resistance characteristics. By virtue of a bias voltage controlled, negative resistance region, bistable action is obtained with a single device in conjunction with a resistive element. However, because the device uses the on-state of the FET where the threshold voltage of the device is exceeded to generate negative resistance, there is a standby power consumption in the order of &mgr;W for the device. Another problem is that oxide is degraded over time because of injection of a significant number of hot carriers into the oxide. Another NRD using a bipolar structure using the reverse base current phenomenon to generate negative resistance is described in U.S. Pat. No. 5,060,194 (Sakai). However, standby power is excessive and in the order of &mgr;W to &mgr;W and this prevents this device from large scale integration. A development to this device is described in U.S. Pat. No. 5,594,683 (Chen). This uses a gated lateral bipolar device structure which reduces the power consumption in comparison with the bipolar device of Sakui. However, the standby power consumption in this device is still of the order of &mgr;W.
SUMMARY OF THE INVENTION
According to the invention, there is provided a negative resistance device comprising:
a semiconductor structure comprising a semiconductor region of one conductivity type termed the bulk, a semiconductor region of second conductivity type termed the source wholly or partially contained in the bulk, a semiconductor region of second conductivity type termed the drain wholly or partially contained in the bulk and a gate region over at least part of the bulk and being insulated from the bulk;
a bias means comprising means for biasing the structure to exhibit negative resistance characteristics, in which:
the source and the gate are each held at a fixed applied potential with respect to to a bulk initial bias and the gate to source applied potential difference is not is not greater than the threshold voltage of the structure;
the drain is held at a fixed applied potential which is of greater magnitude than both the gate applied potential and the source applied potential; and
a variable bias potential is applied to the bulk so that as it is swept towards the source applied potential the bulk current exhibits a negative resistance characteristic.
In one embodiment, the source and the gate have the same applied voltage.
In another embodiment, the semiconductor structure is a MOSFET structure.
In a further embodiment, the structure is fabricated using silicon-on-insulator techniques.
In one embodiment, source doping is equivalent to doping in the bulk so that lateral bipolar current gain is unity.
In another embodiment, the gate is of polysilicon material and is doped with an equivalent level to that of the source.
According to another aspect, the invention provides a memory circuit comprising (a) a negative resistance device as claimed in any preceding claim; and (b) an element which exhibits a positive resistance characteristic connected between the bulk of the device and a terminal having a fixed potential so that two states of the memory circuit at which the current through the resistor matches that through the bulk of the device are stable states for bistable memory operation.
In one embodiment, the bias means comprises an access transistor for the bulk terminal.
In another embodiment, the source diode of the access transistor acts as the positive resistance element
In a further embodiment, the access transistor is of the type having a source, a drain, a gate, and a bulk, the circuit further comprises a load transistor providing a resistive load line, and the source of the access transistor also acts as the bulk of the negative resistance device and the drain of the load transistor.
In one embodiment, said circuit is fabricated on a substrate having a conductivity type different from that of the bulk of the negative resistance device.
In another embodiment, said circuit is fabricated using Silicon On Insulator Techniques.
In a further embodiment, the means of biasing the bulk of the negative resistance device are different from the means of detecting the stored potential in the memory.
Preferably, the means for reading the stored potential is a gain stage.
DETAILED DESCRIPTION OF THE INVENTION
REFERENCES:
patent: 3974486 (1976-08-01), Curtis et al.
patent: 5060194 (1991-10-01), Sakui et al.
patent: 5594683 (1997-01-01), Chen et al.
patent: 5883829 (1999-03-01), van der Wagt
patent: 402262361A- (1990-10-01), None
Concannon Ann
Duane Russell
Mathewson Alan
Jacobson & Holman PLLC
Lam David
National University of Ireland, Cork
Nelms David
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