Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2001-02-22
2002-11-12
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S185180, C365S189070, C327S540000
Reexamination Certificate
active
06480427
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-048249, filed Feb. 24, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a negative-potential detecting circuit and a semiconductor memory device. More specifically, the present invention relates to a negative-potential detecting circuit for use in a power supply system of a semiconductor memory device.
A prior art negative-potential detecting circuit will now be described with reference to FIG.
1
. As
FIG. 1
shows, a negative-potential detecting circuit
10
includes resistance elements R
10
and R
11
and an operational amplifier OP
10
. One end of the resistance element R
10
is connected to a VP power supply for applying a fixed positive potential VP to a semiconductor chip. One end of the resistance element R
11
is connected to the other end of the resistance element R
10
, and the other end thereof is connected to a negative-potential power supply for generating a negative potential VBBO. The operational amplifier OP
10
has an inverted input terminal (−) that receives a potential VO from a node between the resistance elements R
10
and R
11
and a non-inverted input terminal (+) that receives a reference potential Vref. The operational amplifier OP
10
compares the reference potential Vref and the potential VO with each other and detects whether the negative potential VBBO reaches a desired level.
In the prior art negative-potential detecting circuit with the above arrangement, if the resistance elements R
10
and R
11
have their respective resistances r10 and r11, the potential VO applied to the operational amplifier OP
10
is expressed by the following equation:
VO=VBBO+
(
r
11/(
r
10+
r
11))·(
VP−VBBO
)
The resistances r10 and r11 are so determined that the potential VO becomes equal to the reference potential Vref when the negative potential VBBO reaches a desired potential VBB. Thus, the output SVBB of the operational amplifier OP
100
is inverted when the negative potential VBBO reaches VBB. This inversion makes it possible to detect that the negative potential VBBO reaches the desired potential VBB.
However, the prior art negative-potential detecting circuit shown in
FIG. 1
has the following problems:
(1) The precision in detecting the levels is obtained from r11/(r10+r11) of the above equation and it is not higher than 1. Since the potential VO depends on the potential-dividing ratio between the resistance elements R
10
and R
11
, only part of the variation of the negative potential VBBO reflects the potential VO and the detection precision lowers.
(2) The use of the VP power supply increases the number of power supplies in the detecting circuit and thus complicates the circuit itself. Since the positive potential VP needs to be fixed, it is necessary to provide a VP power supply with a structure to charge an external power supply Vcc and keep it at a fixed potential, which complicates the detecting circuit. When a potential difference between VP and VBBO increases, it is likely to exceed the breakdown voltage of a diffusion layer constituting the resistance elements R
10
and R
11
. For this reason, an intermediate potential between the positive and negative potentials VP and VBBO is applied forcibly to a well region surrounding the diffusion layer. A new power supply for applying the intermediate potential is required and the circuit arrangement is complicated accordingly.
(3) Since a transistor having a thick gate oxide and a high breakdown voltage is used in the detecting circuit, the detection sensitivity of the circuit lowers. This results from large variations of the potential VO with the negative potential VBBO. In some cases, the potential VO is set at a high potential close to the positive potential VP when the negative potential VBBO is at a GND level, and it is set at a negative potential lower than the reference potential Vref when the negative potential VBBO is at a highly negative potential. Thus, a transistor having a thick gate oxide and a high breakdown voltage should be used to constitute the operational amplifier OP
10
such that it can cope with the case where the potential VO changes to a negative potential; accordingly, the detecting circuit decreases in detection sensitivity.
In order to resolve the above problems, a negative-potential detecting circuit is proposed in Mihara et al., “A 29 mm2 1.8 V-only 16 Mb DINOR Flash Memory with Gate-Protected Poly-Diode (GPPD) Charge Pump,” ISSCC 99 Digest of Technical Papers, February, 1999, pp 114-115.
FIG. 2
illustrates a negative-potential detecting circuit
20
as proposed in Mihara et al.
The negative-potential detecting circuit
20
includes a PMOS transistor QP
20
, a resistance element R
20
, and an operational amplifier OP
20
. The PMOS transistor QP
20
has a source connected to an external power supply Vcc. One end of the resistance element R
20
is connected to the drain of the PMOS transistor QP
20
, and the other end thereof is connected to a negative-potential power supply for generating a negative potential VBBO. The operational amplifier OP
20
has an inverted input terminal (−) that receives a potential VO from a node between the drain of the PMOS transistor QP
20
and the resistance element R
20
and a non-inverted input terminal (+) that receives a reference potential Vref. The circuit
20
also includes a PMOS transistor QP
21
, a resistance element R
21
, and an operational amplifier OP
21
. The PMOS transistor QP
21
has a source connected to an external power supply Vcc. One end of the resistance element R
21
is connected to the drain of the PMOS transistor QP
21
, and the other end thereof is grounded. The operational amplifier OP
21
has an inverted input terminal (−) that receives a potential VO from a node between the drain of the PMOS transistor QP
21
and the resistance element R
21
and a non-inverted input terminal (+) that receives a reference potential Vref. The output terminal of the operational amplifier OP
21
is connected to the gates of the PMOS transistors QP
20
and QP
21
.
In the above negative-potential detecting circuit so arranged, the node between the PMOS transistor QP
21
and the resistance element R
21
is maintained at the reference potential Vref. The PMOS transistors QP
21
and QP
20
thus serve as a constant-current source
21
for supplying a constant current
I′
(=Vref/r21:r21 is a resistance of the resistance element R
21
). If a desired detection level of the negative potential VBBO is VBB, the resistance r20 of the resistance element R
20
is expressed as follows: r20=(1 −VBB/Vref)·r21. Thus, the voltage VO at the node between the drain of the PMOS transistor QP
20
and the resistance element R
20
is given as follows: VO=VBBO+Vref−VBB.
Assuming that the desired detection potential VBB is −2.5 V and the reference potential Vref is 1.25V, −VBB/Vref is 2 and thus r20 becomes equal to 3r21. Considering a voltage drop in the resistance element R
20
, R
20
·I′ is 1.25 V and thus 3r20 ·I′ becomes equal to 3.75V. If the potential VO=1.25V=Vref, the negative potential VBBO must be −2.5 V that is equal to the desired detection potential VBB.
The above negative-potential detecting circuit of Mihara et al. has the following advantages over the circuit shown in FIG.
1
:
(1) The precision of the detection level is 1 (=&Dgr;VO/&Dgr;VBBO). The precision is high because the potential VO is directly influenced by variations of the negative potential VBBO.
(2) Since no VP power supplies are required, the circuit arrangement can be simplified and the problem of a breakdown voltage of a diffusion layer constituting the resistance elements can be resolved.
The upper limit of the potential VO is Vcc. In some cases, however, the lower limit of the potential VO
Banner & Witcoff , Ltd.
Ho Hoai
Kabushiki Kaisha Toshiba
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