Negative feedback to reduce voltage oscillation in CMOS output b

Details Negative feedback to reduce voltage oscillation in CMOS output b Negative feedback to reduce voltage oscillation in CMOS output b

1994-12-19

1995-12-05

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326121, 327380, H03K 1716

Patent

active

054732638

ABSTRACT:
A CMOS output buffer circuit includes negative feedback means for significantly reducing voltage oscillation. The buffer circuit is comprised of a pull-up transistor (P1), a pull-down transistor (N1), a first reference voltage generator circuit (44), a second reference voltage generator circuit (54), a first negative feedback circuit (48), and a second negative feedback circuit (58). First and second negative feedback circuits are coupled between the internal power supply potential/ground potential nodes and the gates of the pull-up/pull-down driver transistors so as to reduce the rate of change of the transient charging/discharging currents, respectively.

REFERENCES:
patent: 4973861 (1990-11-01), Dikken
patent: 5028817 (1991-07-01), Patil
patent: 5153457 (1992-10-01), Martin
patent: 5248906 (1993-07-01), Mahmood
patent: 5248907 (1993-09-01), Lin
patent: 5315187 (1994-05-01), Cheng

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