Negative differential resistance pull up element for DRAM

Static information storage and retrieval – Systems using particular element – Negative resistance

Reexamination Certificate

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C365S189110, C365S149000, C365S204000, C365S222000, C257S369000, C257SE27002

Reexamination Certificate

active

07995380

ABSTRACT:
A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.

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