Narrow width trenches for field isolation in integrated circuits

Details Narrow width trenches for field isolation in integrated circuits Narrow width trenches for field isolation in integrated circuits

1996-04-04

1998-04-21

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257371, 257372, H01L 2900, H01L 2976, H01L 2994

Patent

active

057420904

ABSTRACT:
An integrated circuit device has a plurality of active devices which are formed on a semiconductor body. A plurality of narrow isolating regions of insulating material are vertically formed on the semiconductor body such that at least one of the narrow isolating regions separates and thereby isolates adjacent active devices. Essentially all of said isolating regions are substantially equal in width, preferably less than or equal to about 0.5 .mu.m.

REFERENCES:
patent: 4211582 (1980-07-01), Horng et al.
patent: 4905065 (1990-02-01), Selcuk et al.
patent: 4922318 (1990-05-01), Thomas et al.
patent: 5445989 (1995-08-01), Lur et al.
patent: 5445990 (1995-08-01), Yook et al.
patent: 5457339 (1995-10-01), Komori et al.
patent: 5459096 (1995-10-01), Venkatesan et al.
patent: 5460998 (1995-10-01), Liu
patent: 5466623 (1995-11-01), Shimize et al.
patent: 5468675 (1995-11-01), Kaigawa
patent: 5468676 (1995-11-01), Madan
patent: 5470783 (1995-11-01), Chiu et al.
patent: 5472904 (1995-12-01), Figura et al.
patent: 5472905 (1995-12-01), Paek et al.
patent: 5472906 (1995-12-01), Shimizu et al.
patent: 5473186 (1995-12-01), Morita
patent: 5474953 (1995-12-01), Shimizu et al.
Dennehy, William J., "Non-Lutching Integrated Circuits", RCA Technical Notes No. 876, 12 Feb. 1971 (4 pp.).
Fuse, Genshu; Fukumoto, Masanori; Shinohara, Akihira; Odanaka, Shinji; Sasago, Masaru and Ohzone, Takashi, "A New Isolation Method with Boron-Implanted Sidewalls for Controlling Narrow-Width Effect" IEEE Transactions On Electron Devices, vol. ED-34, No. 2, Feb., 1987.
Sawada, Shizuo; Higuchi, Takayoshi; Mizuno, Tomohisa; Shinozaki, Satoshi and Ozawa, Osamu, "Electrical Properties for MOS LSI's Fabricated Using Stacked Oxide SWAMI Technology" IEEE Transactions on Electron Devices, vol. ED-32, No. 11, Nov. 1985.
Wolf Ph.D., Stanley, Chapter 6.6.7 "Trench Isolation for CMOS", Silicon Processing for the VLSI Era--vol. 3: The Submicron Mosfet, pp. 406-413, 1995.
Wolf Ph.D., Stanley, Chapter 2 "Isolation Technologies for Integrated Circuits", Silicon Processing for the VLSI Era--vol. 2: Process Integration, pp. 12-69, 1990.

Affiliated with

Also associated with

Rating

Narrow width trenches for field isolation in integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Narrow width trenches for field isolation in integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Narrow width trenches for field isolation in integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2060520