Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-04-10
2007-04-10
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
11299264
ABSTRACT:
A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.
REFERENCES:
patent: 4638431 (1987-01-01), Nishimura
patent: 5123095 (1992-06-01), Papadopoulos et al.
patent: 6816960 (2004-11-01), Koyanagi
Bailey Neil
Barlow Stephen
Plowman David
Ramsdale Timothy
Swann Robert
Broadcom Corporation
Ellis Kevin L.
McAndrews Held & Malloy Ltd.
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