Narrow contact design for magnetic random access memory...

Details Narrow contact design for magnetic random access memory... Narrow contact design for magnetic random access memory...

2002-02-22

2003-05-20

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetic thin film

C365S171000, C365S158000, C365S066000, C365S055000

Reexamination Certificate

active

06567300

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to magnetic random access memory (MRAM) devices.
BACKGROUND OF THE INVENTION
Semiconductors are used for integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM) and flash memory, which use a charge to store information.
A more recent development in memory devices involves spin electronics, which combines semiconductor technology and magnetics. The spin of an electron, rather than a charge, is used to indicate the presence of a “1” or “0”. One such spin electronic device is a magnetic random-access memory (MRAM), which includes conductive lines positioned perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack. The place where the conductive lines intersect is called a cross-point. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces the magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a “0” or “1”, is storable in the alignment of magnetic moments. The resistance of the magnetic component depends on the moment's alignment. The stored state is read from the element by detecting the component's resistive state. A memory cell may be constructed by placing the conductive lines and cross-points in a matrix structure having rows and columns.
An advantage of MRAMs compared to traditional semiconductor memory devices such as DRAMs is that MRAMs are non-volatile. For example, a personal computer (PC) utilizing MRAMs would not have a long “boot-up” time, as with conventional PCs that utilize DRAMs. Also, an MRAM does not need to be powered up and has the capability of “remembering” stored data without continually requiring a refresh operation.
MRAM devices operate differently than traditional memory devices, and they introduce design and manufacturing challenges. For example, because a significantly high amount of voltage must be placed on the conductive lines to achieve a current high enough to switch the resistive state of the memory elements, leakage currents can occur from one resistive memory element to neighboring resistive memory elements. While it is unlikely that leakage current will cause switching of neighboring memory elements, leakage current is problematic in that the amount of current that leaks away is lost for the switching process for the intended memory cell. Furthermore, during a reading operation, neighboring resistors or memory elements may act as parallel resistors, thus weakening the signal from the element that is being read.
SUMMARY OF THE INVENTION
Preferred embodiments of the present invention achieve technical advantages as an MRAM device having conductive lines with smaller widths than in prior art MRAMs. The narrower conductive lines are used to switch and read out the memory cell information. In one direction of the array, the conductive lines have a smaller width than the width of the resistive memory elements, so that the resistive memory elements are not fully contacted by the conductive lines.
In one embodiment, a resistive semiconductor device includes a plurality of first conductive lines positioned parallel to one another in a first direction, a plurality of resistive memory elements disposed over the first conductive lines, and a plurality of second conductive lines disposed over the resistive memory elements. The second conductive lines are positioned parallel to one another in a second direction, and the second conductive lines partially contact the resistive memory elements.
In another embodiment, an MRAM semiconductor device includes a semiconductor substrate, a plurality of first conductive lines disposed over the substrate, the first conductive lines positioned parallel to one another in a first direction, and a plurality of resistive memory elements disposed over the first conductive lines. A plurality of second conductive lines are disposed over the resistive memory elements. The second conductive lines are positioned parallel to one another in a second direction, and the second conductive lines partially contact the resistive memory elements.
In another embodiment, a method of manufacturing an MRAM semiconductor device includes providing a semiconductor substrate, forming a plurality of a plurality of first conductive lines parallel to one another in a first direction over the substrate, disposing a plurality of resistive memory elements over the first conductive lines, and forming a plurality of second conductive lines over the resistive memory elements. The second conductive lines are positioned parallel to one another in a second direction, and the second conductive lines partially contact the resistive memory elements.
Advantages of embodiments of the invention include reducing the contact area of the second conductive lines to the resistive memory elements, reduced leakage currents, and a reduction in the number of errors and failures. Another advantage includes the ability to have wordlines and bitlines having the same widths, rather than having varying widths as in prior art magnetic memory devices, which results in a more uniform pattern from a processing perspective, simplifying the manufacturing process. The speed of a memory device may be increased, because of the reduced resistance of the memory cells resulting from the smaller number of cells being connected to the conductive lines.


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patent: 6331944 (2001-12-01), Monsma et al.
patent: 6404673 (2002-06-01), Matsui

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