Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2007-03-06
2007-03-06
Doan, Theresa T. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000, C438S283000
Reexamination Certificate
active
10754540
ABSTRACT:
A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.
REFERENCES:
patent: 6225173 (2001-05-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 6472258 (2002-10-01), Adkisson et al.
patent: 6475869 (2002-11-01), Yu
patent: 6475890 (2002-11-01), Yu
patent: 6583469 (2003-06-01), Fried et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6764884 (2004-07-01), Yu et al.
patent: 6787854 (2004-09-01), Yang et al.
patent: 6855989 (2005-02-01), Wang et al.
patent: 2002/0093053 (2002-07-01), Chan et al.
patent: 2002/0130354 (2002-09-01), Sekigawa et al.
patent: 2002/0153587 (2002-10-01), Adkisson et al.
patent: 2002/0177263 (2002-11-01), Hanafi et al.
patent: WO 4/068589 (2004-08-01), None
patent: WO 04/093181 (2004-10-01), None
Copy of International Search Report dated Mar. 4, 2005.
Digh Hisamoto et al., “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-pending U.S. Appl. No. 10/726,619, filed Dec. 4, 2003, entitled: “Damascene Gate Semiconductor Processing with Local Thinning of Channel Region,” 20 page specification, 12 sheets of drawings.
Co-pending U.S. Appl. No. 10/405,342, filed Apr. 3, 2003, entitled: “Method for Forming a Gate in a FinFET Device and Thinning a Fin in a Channel Region of the FinFET Device,” 17 page specification, 14 sheets of drawings.
Ahmed Shibly S.
Wang Haihong
Yu Bin
Advanced Micro Devices , Inc.
Doan Theresa T.
Harrity & Snyder LLP
LandOfFree
Narrow-body damascene tri-gate FinFET does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Narrow-body damascene tri-gate FinFET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Narrow-body damascene tri-gate FinFET will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3756428