Nanotube logic circuits

Electronic digital logic circuitry – Function of and – or – nand – nor – or not

Reexamination Certificate

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C257S211000

Reexamination Certificate

active

07911234

ABSTRACT:
A logic cell that is immune to misaligned carbon nanotubes. Carbon nanotubes are positioned on a substrate. Contacts are formed on a layer of carbon nanotubes, including a first input contact, a second input contact, an output contact, a first gate region, and a second gate region. The output contact is positioned between the first input contact and the second input contact, and a cell region is provided bounded by a width of the output contact and residing between the first input contact and the second input contact. A nonconductive region is positioned in the layer of carbon nanotubes between any two or more of the plurality of contacts that, if shorted, would inhibit a logic function.

REFERENCES:
patent: 4763289 (1988-08-01), Barzilai et al.
patent: 6691286 (2004-02-01), McElvain et al.
patent: 6707098 (2004-03-01), Hofmann et al.
patent: 6781166 (2004-08-01), Lieber et al.
patent: 6798000 (2004-09-01), Luyken et al.
patent: 6820244 (2004-11-01), Lincoln
patent: 6972467 (2005-12-01), Zhang et al.
patent: 6990009 (2006-01-01), Bertin et al.
patent: 7265575 (2007-09-01), Bertin
patent: 7541842 (2009-06-01), Bertin et al.
patent: 7564269 (2009-07-01), Bertin
patent: 7582534 (2009-09-01), Afzali-Ardakani et al.
patent: 2003/0058697 (2003-03-01), Tour et al.
patent: 2004/0238887 (2004-12-01), Nihey
patent: 2005/0035786 (2005-02-01), Bertin et al.
patent: 2007/0141762 (2007-06-01), Hyde et al.
patent: 2007/0205450 (2007-09-01), Okita
Atienza, David et al., “System-Level Design for Nano-Electronics,” 14th IEEE International Conference in Electronics, Circuits and Systems (ICECS), 2007, pp. 747-751, Morocco, IEEE.
Banerjee, Kaustav et al., “Are Carbon Nanotubes the Future of VLSI Interconnections?,” Design Automation Conference, 2006, pp. 809-814, San Francisco, CA, ACM.
Beer, Ilan et al., “RuleBase: An Industry-Oriented Formal Verification Tool,” Proc. Design Automation Conference, 1996.
Butts, Michael et al., “Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips,” International Conference on Computer-Aided Design, Nov. 2002, pp. 1-8.
Chen, Jia et al., “Air-Stable Chemical Doping of Carbon Nanotube Transistors,” Device Research Conference, Jun. 21-23, 2004, 62nd DRC, Conference Digest, pp. 137-138.
Collins, Philip G. et al., “Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown,” Science, Apr. 27, 2001, pp. 706-708, vol. 292.
Dehon, Andre et al., “Seven Strategies for Tolerating Highly Defective Fabrication,” IEEE Design & Test of Computers, 2005, pp. 306-315, vol. 22, No. 4, IEEE.
Deng, Jie et al., “Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections,” 2007 IEEE International solid-State Circuits Conference, 2007, pp. 70-71 and 588, IEEE.
Deng, Jie et al., “A Circuit-Compatible SPICE Model for Enhancement Mode Carbon Nanotube Field Effect Transistors,” Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices, 2006, pp. 166-169, IEEE.
Dwyer, C. et al., “Design Tools for a DNA-Guided Self-Assembling Carbon Nanotube Technology,” Nanotechnology, 2004, pp. 1240-1245, vol. 15, No. 9, United Kingdom, IOP Publishing Ltd.
Fuhrer, M. S. et al., “Crossed Nanotube Junctions,” Science, Apr. 21, 2000, pp. 494-497, vol. 288.
Goldstein, Seth Copen et al., “NanoFabrics: Spatial Computing Using Molecular Electronics,” Proceedings of the 28th Annual International Symposium on computer Architecture, Jun. 2001, pp. 178-191.
Han, Song et al., “Template-Free Directional Growth of Single-Walled Carbon Nanotubes on a- and r-Plane Sapphire,” Journal of the American Chemical Society, Mar. 22, 2005, pp. 5294-5295, vol. 127, No. 15, Washington DC, American Chemical Society.
He, Chen et al., “Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 20007, pp. 817-833, vol. 26, No. 5, IEEE.
Javey, Ali et al., “Ballistic Carbon Nanotube Field-Effect Transistors,” Nature, Aug. 7, 2003, pp. 654-657, vol. 424, Nature Publishing Group.
Javey, Ali et al., “High Performance n-Type Carbon Nanotube Field-Effect Transistors with Chemically Doped Contacts,” Nano Letters, 2005, pp. 345-348, vol. 5, No. 2, American Chemical Society.
Kang, Seong Jun et al., “High-performance Electronics Using Dense, Perfectly Aligned Arrays of Single-walled Carbon Nanotubes,” Nature Nanotechnology, Apr. 2007, pp. 230-236, vol. 2, Nature Publishing Group.
Kocabas, C. et al., Nano Letters, Mar. 30, 2007, pp. 1195-1202, vol. 7, No. 5, Washington DC, American Chemical Society.
Kocabas, Coskun et al., “Spatially Selective Guided Growth of High-Coverage Arrays and Random Networks of Single-Walled Carbon Nanotubes and Their Integration into Electronic Devices,” Journal of the American Chemical Society, Mar. 22, 2006, pp. 4540-4541, vol. 128, No. 14, Washington DC, American Chemical Society.
Li, Xiaolin et al., “Chemically Derived, Ultrasmooth Graphene Nanoribbon Semiconductors,” Science, Feb. 29, 2008, p. 1229-1232, vol. 319.
Li, Yiming et al., “Preferential Growth of Semiconducting Single-Walled Carbon Nanotubes by a Plasma Enhanced CVD Method,” Nano Letters, Jan. 22, 2004, pp. 317-321, vol. 4, No. 2, Washington DC, American Chemical Society.
Nepal, K. et al., “Optimizing Noise-Immune Nanoscale Circuits using Principles of Markov Random Fields,” Proc. Great Lakes Symposium on VLSI, 2006, pp. 149-152.
Patil, Nishant et al., “Integrated Wafer-Scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures,” 2008 Symposium on VLSI Technology Digest of Technical Papers, 2008, pp. 205-206, IEEE.
Paul, Bipul C. et al., “Modeling and Analysis of Circuit Performance of Ballistic CNFET,” Proc. Design Automation Conference, 2006, pp. 717-722, ACM.
Rachlin, Eric et al., “Nanowire Addressing with Randomized-Contact Decoders,” Proc. Intl. Conf. CAD, 2006, ACM.
Rad, Reza M. P. et al., “A New Hybrid FPGA with Nanoscale Clusters and CMOS Routing,” Proc. Design Automation Conference, 2006, pp. 727-730, ACM.
Rao, Wenjing et al., “Fault Tolerant Nanoelectronic Processor Architectures,” Proc. Asia South Pacific Design Automation Conference, 2005, pp. 311-316.
Raychowdhury, Arijit et al., “Modeling of Ballistic Carbon Nanotube field Effect Transistors for Efficient Circuit Simulation,” Proc. Intl. Conf. CAD, 2003, pp. 487-490, ACM.
Snider, Greg et al., “CMOS-Like Logic in Defective, Nanoscale Crossbars,” Nanotechnology, 2004, pp. 881-891, vol. 15, United Kingdom, IOP Publishing Ltd.
Strukov, Dmitri B. et al., Defect-Tolerant Architectures for Nanoelectronic Crossbar Memories, Journal of Nanoscience and Nanotechnology, Aug. 2006.
Tahoori, Mehdi B., “Application-Independent Defect-Tolerant Crossbar Nano-Architectures,” ACM Journal Emerging Technologies in Computing, 2006, ACM.
Wang, Zhanglei et al., “Using built-in Self-Test and Adaptive Recovery for Defect Tolerance in Molecular Electronics-Based Nanofabrics,” Proc. International Test Conference, 2005, Paper 21.1, pp. 477-486, IEEE.
Wong, H.-S. P. et al., “Carbon Nanotube Field Effect Transistors—Fabrication, Device Physics, and Circuit Implications,” Proc. 2003 IEEE International Solid-State Circuits Conference, 2003, pp. 370-371, IEEE.
Zhang, Guangyu et al., “Selective Etching of Metallic Carbon Nanotubes by Gas-Phase Reaction,” Science, Nov. 10, 2006, pp. 974-977, vol. 314.
Zhang, Jie et al., “Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,” Design Automation and Test in Europe, 2008, EDAA.
Zhang, Rui et al., &

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