Nanoscale patterning for the formation of extensive wires

Details Nanoscale patterning for the formation of extensive wires Nanoscale patterning for the formation of extensive wires

2000-03-01

2001-09-25

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S689000, C438S735000, C438S738000

Reexamination Certificate

active

06294450

ABSTRACT:

BACKGROUND ART
With the constantly decreasing feature sizes of integrated-circuit devices, the need for increasingly fine, lithographically-defined patterning is limiting further advances of the technology. Consequently, a growing amount of effort is being devoted to self-assembly techniques to form nanoscale switching elements; see, e.g., C. P. Collier et al, “Electronically Configurable Molecular-Based Logic Gates”,
Science
, Vol. 285, pp. 391-394 (Jul. 16, 1999). The self-assembled switching elements may be integrated on top of a Si integrated circuit so that they can be driven by conventional Si electronics in the underlying substrate. To address the switching elements, nanoscale interconnections or wires, with widths less than 10 &mgr;m and lengths exceeding 1 &mgr;m, are needed. The self-assembled wires connecting the conventional electronics to the self-assembled switching elements should be anchored at locations defined by the underlying circuitry and should be composed of materials compatible with Si integrated-circuit processing.
Recent reports have shown that catalytic decomposition of a Si-containing gas by a metal, such as Au or Fe, can form long “nanowires”; see, e.g., J. Westwater et al, “Growth of silicon nanowires via gold/silane vapor-liquid-solid reaction”,
Journal of Vacuum Science and Technology B
, Vol. 15, pp. 554-557 (May/June 1997) and A. M. Morales et al, “A Laser Ablation Method for the Synthesis of Crystalline Semiconductor Nanowires”,
Science
, Vol. 279, pp. 208-211 (Jan. 9, 1998). These studies were based an earlier-developed technique frequently called the vapor-liquid-solid (VLS) mechanism. A liquid alloy droplet containing the metal and Si is located at the tip of the wire and moves along with the growing end of the wire. The wires may either be formed in the gas phase or anchored at one end on a substrate; see, e.g., J. L.
Liu et al, “Gas-source MBE growth of freestanding Si nano-wires on Au/Si substrate”,
Superlattices and Microstructures
, Vol. 25, No. 1/2, pp. 477-479 (1999). However, Au and Fe migrate into Si rapidly and create deep levels, which can degrade devices, such as addressing circuitry and other portions of the system formed by conventional Si integrated-circuit technology.
Titanium and TiSi
2
are compatible with integrated-circuit technology and are frequently used in Si circuits to reduce resistance of silicon and polycrystalline-silicon conducting regions. Although Ti forms deep levels in Si, its solubility and diffusion coefficient in Si are low, and the deep levels are not at mid-gap. With suitable handling, Ti is generally accepted in integrated-circuit facilities.
Long, thin “nanowires” of silicon or other materials, such as carbon, can be formed by catalyst-enhanced reaction of gaseous precursors; see, e.g., the above-mentioned patent application Ser. No. 09/282,048. The catalysts are often metal-containing nanoparticles either on the surface of a substrate or suspended in the reactor ambient. The nanowires may be usefull in electronic or other devices as either connections to an electronic element such as a switch or as electronic elements themselves; see, e.g., the above-mentioned patent applications Ser. Nos. 09/280,225, 09/282,045, 09/699,080 and 09/699,269, and U.S. Pat. No. 6,128,214. However, it is difficult to control the placement of these freestanding wires, and therefore it is difficult to use these nanowires in real integrated circuits.
The fabrication of nanowires is important for device applications, such as logic circuits, crossbar memories, etc. Two lithographic fabrication approaches that have been used on larger scale devices include electron beams and X-rays. The typical size of an electron beam is about 20 nm, and would require rastering the beam over a surface. The typical size of an X-ray beam is about 50 nm, and there are no lenses available to focus an X-ray beam. Also, the use of X-rays requires a synchrotron, and thus is very expensive. Neither approach permits generation and use of a beam on the order of 10 nm, which is required for nanowire fabrication.
In either event, it is not presently possible to achieve critical dimensions in patterning down to 10 nm. The present invention solves this problem, enabling the fabrication of nanowires with widths below 10 nm and with lengths extending into microscale dimensions, thereby avoiding the difficulties of rastering and the cost of a synchrotron, while permitting more accurate control of the placement of the nanowires.
DISCLOSURE OF INVENTION
In accordance with the present invention, a method is provided for forming a platen useful for forming nanoscale wires for device applications. The method comprises:
(a) providing a substrate having a major surface;
(b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate;
(c) cleaving the stack normal to the major surface to expose the plurality of alternating layers; and
(d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology.
The pattern of the platen is then transferred into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing.
Also in accordance with the present invention, a nano-imprinting device, or platen, comprises a plurality of alternating layers of the two dissimilar materials, with the layers of one material etched relative the layers of the other material to form indentations of the one material. Each material independently has a thickness within a range of about 0.4 nm to several hundred nm. The device is then oriented such that the indentations are parallel to a surface to be imprinted and the pattern created by the indentations is imprinted into the surface.
The fabrication of nanowires disclosed and claimed herein avoids most, if not all, of the problems of the prior art.


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C.P. Collier et al, “Electronically configurable Molecular-Based Logic Gates”, Science, vol. 285, pp. 391-394 (Jul. 16, 1999).
J. Westwater et al, “Growth of silicon nanowires via gold/silane vapor-liquid-solid reaction”, Journal of Vacuum Science and Technology B, vol. 15, pp. 554-557 (May/Jun. 1997).
A.M. Morales et al, “A Laser Ablation Method for the Synthesis of Crystalline Semiconductor Nanowires”, Science, vol. 279, pp. 208-211 (Jan. 9, 1998).
J.L. Liu et al, “Gas-source MBE growth of freestanding Si nano-wires on Au/Si substrate”, Superlattices and Microstructures, vol. 25, pp. 477-479 (1999).
X. Sun et al, “Multilayer resist methods for nanoimprint lithography on nonflat surfaces”, Journal of Vacuum Science and Technology, vol. B16, No. 6, pp. 3922-3925 (1998).
Z. Lilienthal-Weber et al, “Spontaneous Ordering in Bulk GaN:Mg Samples”, Physical Review Letters, vol. 83, No. 12, pp. 2370-2373 (Sep. 20, 1999).

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