Nanoscale interconnection interface

Details Nanoscale interconnection interface Nanoscale interconnection interface

2005-04-26

2008-03-25

Lamarre, Guy J. (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S752000, C714S805000, C716S030000, C716S030000, C708S001000

Reexamination Certificate

active

07350132

ABSTRACT:
One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2kor fewer nanowires, employing supplemental, internal address lines to map 2knanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2knanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2knanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

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