Nanoscale floating gate and methods of formation

Details Nanoscale floating gate and methods of formation Nanoscale floating gate and methods of formation

2006-08-09

2010-02-23

Coleman, W. David (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S264000, C257SE21422, C977S721000, C977S762000

Reexamination Certificate

active

07667260

ABSTRACT:
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

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