Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-08
2002-04-09
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185170, C365S185280
Reexamination Certificate
active
06370062
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of operating the same, and more particularly, to a NAND-type flash memory device and a method of operating the same.
2. Description of the Related Art
Flash memory devices maintain information stored in their memory cells even if their power supply is interrupted. Therefore, flash memory devices are widely used in computers and memory cards.
Flash memory devices are classified as NOR-type flash memory devices and NAND-type flash memory devices. NOR-type flash memory devices have a high sensing margin because they can obtain larger cell current than NAND-type flash memory devices, but they have low integration density. Accordingly, NAND-type flash memory devices are widely used when high integration density is required.
FIG. 1
is a block diagram of a typical NAND-type flash memory device.
Referring to
FIG. 1
, the NAND-type flash memory device includes a cell array area (C/A)
100
in which a plurality of memory cell transistors are arranged in a matrix. A row decoder (R/D)
300
and a column decoder (C/D)
500
, which operate the plurality of memory cell transistors, are disposed around the C/A
100
. The C/D
500
includes a sense amplifier (S/A) for amplifying a signal output from the C/A
100
. The R/D
300
and the C/D
500
are controlled by an input/output unit (I/O)
700
. The I/O
700
processes signals received via a plurality of pads and determines the operation mode, for example, a program mode, an erase mode or a read mode, of the flash memory device. The I/O
700
also outputs signals for selecting desired cells or blocks within the C/A
100
. The signals output from the I/O
700
are converted into signals for selecting desired cells or blocks within the C/A
100
by the R/D
300
and the C/D
500
. The I/O
700
also has a function of outputting cell information, which is amplified by the S/A in a read mode, to the outside.
FIG. 2
is a circuit diagram partially showing a row decoder and a cell array area, which construct a conventional NAND-type flash memory device. Referring to
FIG. 2
, a cell array area
100
a
is composed of a plurality of cell blocks, and each cell block includes a plurality of strings, i.e., m strings S
1
through Sm. Each string is interposed between a single bit line BL and a common source line CS. For example, a first string S
1
is interposed between a first bit line BL
1
and the common source line CS, and an m-th string Sm is interposed between an m-th bit line BLm and the common source line CS. A single string is composed of a single string select transistor SST, a plurality of cell transistors C and a single ground select transistor GST. For example, the first string S
1
is composed of a first string select transistor SST
1
, a first ground select transistor GST
1
and n cell transistors C
11
, C
12
, C
13
, . . . , and C
1
n, which are connected in series between the first string select transistor SST
1
and the first ground select transistor GST
1
. The first string select transistor SST
1
is connected to the first bit line BL
1
, and the first ground select transistor GST
1
is connected to the common source line CS. Similarly, the m-th string Sm is composed of an m-th string select transistor SSTm, an m-th ground select transistor GSTm and n cell transistors Cm
1
, Cm
2
, Cm
3
, . . . , and Cmn, which are connected in series between the m-th string select transistor SSTm and the m-th ground select transistor GSTm. The m-th string select transistor SSTm is connected to the m-th bit line BLm, and the m-th ground select transistor GSTm is connected to the common source line CS.
A cell block constructed by the m strings S
1
through Sm includes a single string select line SSL, n word lines WL
1
, WL
2
, WL
3
, . . . , and WLn and a single ground select line GSL. The string select line SSL is connected to the gate electrodes of the first through m-th string select transistors SST
1
through SSTm. The ground select line GSL is connected to the gate electrodes of the first through m-th ground select transistors GST
1
through GSTm. The first word line WL
1
is connected to the control gate electrodes of the first cell transistors C
11
through Cm
1
of the respective strings S
1
through Sm. The second word line WL
2
is connected to the control gate electrodes of the second cell transistors C
12
through Cm
2
of the respective strings S
1
through Sm. Similarly, the third word line WL
3
is connected to the control gate electrodes of the third cell transistors C
13
through Cm
3
, and the n-th word line WLn is connected to the control gate electrode of the n-th cell transistors C
1
n through Cmn of the respective strings S
1
through Sm.
A conventional row decoder
300
a
includes a single string control line SCL, n word control lines W
1
, W
2
, W
3
, . . . , and Wn, a single ground control line GCL and a plurality of block drivers. A single block driver controls only one cell block. For example, a block driver
310
controls only one cell block which is composed of the first through m-th strings S
1
through Sm. The block driver
310
is composed of a single string driver transistor SDT, n word driver transistors WDT
1
through WDTn and a single ground driver transistor GDT. The string driver transistor SDT is interposed between the string control line SCL and the string select line SSL, and the ground driver transistor GDT is interposed between the ground control line GCL and the ground select line GSL. The first word driver transistor WDT
1
is interposed between the first word control line W
1
and the first word line WL
1
, and the second word driver transistor WDT
2
is interposed between the second word control line W
2
and the second word line WL
2
. Similarly, the third word driver transistor WDT
3
is interposed between the third word control line W
3
and the third word line WL
3
, and the n-th word driver transistor WDTn is interposed between the n-th word control line Wn and the n-th word line WLn. The block driver
310
also includes a single driver control line DCL which is connected to the gate electrodes of the string driver transistor SDT, the n word driver transistors WDT
1
through WDTn and the ground driver transistor GDT.
The following description concerns a method of operating the conventional NAND-type flash memory device of FIG.
2
.
When a desired cell transistor, for example, the second cell transistor C
12
of the first string S
1
, in the cell array area
100
a
is intended to be selectively programmed, a voltage of 0 volts is applied to a semiconductor substrate with the cell array area
100
a
, that is, to the bulk areas of the cell transistors and the common source line CS. In addition, a voltage of 0 volts is applied to the first bit line BL
1
connected to the first string S
1
and the ground control line GCL. In this case, a program inhibition Vpi, for example, a power voltage Vcc, is applied to the second through m-th bit lines BL
2
, . . . , BLm, i.e., the unselected bit lines. A power voltage Vcc is applied to the string control line SCL, and a program voltage V
PGM
of about 20 volts is applied to the second word control line W
2
. A voltage of 0 volts is applied to the first and third word control lines W
1
and W
3
, and a pass voltage V
PASS
of about 11 volts is applied to the fourth through n-th word control lines W
4
, . . . , Wn. A voltage, which is higher than the program voltage V
PGM
applied to the second word control line W
2
, i.e., a voltage of V
PGM
+&agr;, is applied to the driver control line DCL to completely turn on the second word driver transistor WDT
2
. Here, the voltage &agr; must be higher than the threshold voltage of the second word driver transistor WDT
2
.
As described above, to program the conventional NAND-type flash memory device, a high voltage higher than a program voltage should be applied to the driver control line DCL of the block driver
310
for controlling the selected cell block. As a result, the string driver transistor
Mai Son
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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