NAND non-volatile two-bit memory and fabrication method

Details NAND non-volatile two-bit memory and fabrication method NAND non-volatile two-bit memory and fabrication method

2006-05-04

2009-06-16

Nguyen, Dao H (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S319000, C257SE21680, C257SE21690, C438S257000, C438S278000

Reexamination Certificate

active

07547941

ABSTRACT:
A NAND non-volatile two-bit memory cell comprises a cell stack and two select stacks disposed on an active area of a substrate. Each select stack is respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stack. The cell stack has four components: a first dielectric layer disposed over the substrate; a charge accumulation layer capable of holding charge in a portion thereof to store information and disposed over the first dielectric layer; a second dielectric layer disposed over the charge accumulation layer; and a control gate disposed over the second dielectric layer. The select stack has two components: a third dielectric layer disposed over the substrate and a select gate, capable of inverting an underneath channel region to function as a source or a drain of the memory cell, disposed over the third dielectric layer.

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