NAND memory cells

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S324000, C257S510000, C257SE21214, C257SE21423, C257SE29165

Reexamination Certificate

active

07973353

ABSTRACT:
A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.

REFERENCES:
patent: 6713834 (2004-03-01), Mori et al.
patent: 6746918 (2004-06-01), Wu
patent: 7348236 (2008-03-01), Abbott et al.
patent: 2005/0285178 (2005-12-01), Abbott et al.

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