NAND memory arrays

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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Details

C438S257000, C438S266000, C438S211000

Reexamination Certificate

active

07419895

ABSTRACT:
Methods and apparatus are provided. A source slot and a drain contact region are formed at opposite ends of a NAND string disposed on a substrate of a NAND memory array using a single mask. The drain contact region is self-aligned to a drain select gate. The NAND string has a plurality of memory cells connected in series.

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patent: 7075140 (2006-07-01), Spadea
patent: 2002/0149081 (2002-10-01), Goda
patent: 2005/0040444 (2005-02-01), Cohen

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