NAND interface

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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Details

C365S189040, C365S230010, C365S233120, C365S233180

Reexamination Certificate

active

07916557

ABSTRACT:
A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin adapted to receive all commands and addresses, and data communication is performed on a number of data communication pins.

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patent: 6519194 (2003-02-01), Tsujino et al.
patent: 6611935 (2003-08-01), Landry
patent: 7038946 (2006-05-01), Hosono et al.
patent: 7130958 (2006-10-01), Chou et al.
patent: 7167411 (2007-01-01), Ahn
patent: 7296143 (2007-11-01), Gaskins et al.
patent: 2006/0067123 (2006-03-01), Jigour et al.
patent: 1424635 (2004-06-01), None
patent: 1764803 (2007-03-01), None

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