NAND flash memory device with burst read latency function

Details NAND flash memory device with burst read latency function NAND flash memory device with burst read latency function

2006-08-29

2009-10-27

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S233180, C365S233170, C365S189050, C365S239000, C365S189150

Reexamination Certificate

active

07609553

ABSTRACT:
A NAND flash memory device may include an interface block which receives an external read enable signal to output an internal clock signal during a read operation. The NAND flash memory device may also include a buffer clock controlling circuit which operates in response to a data output enable signal and the internal clock signal. The NAND flash memory device may also include a buffer clock generating circuit which receives the internal clock signal and which generates first and second buffer clock signals according to a control output of the buffer clock control circuit. The NAND flash memory device may also include a data output buffer circuit which sequentially outputs read data in response to one of the first and second buffer clock signals, wherein the buffer clock controlling circuit controls the buffer clock generating circuit to generate the second buffer clock signal having a single pulse when the data output enable signal is activated.

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