NAND flash memory cell row

Details NAND flash memory cell row NAND flash memory cell row

2006-02-28

2006-02-28

Tran, Mai-Huong (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S316000, C257S321000, C257S438000, C438S260000, C438S267000, C438S254000, C438S257000, C438S253000, C438S259000

Reexamination Certificate

active

07005699

ABSTRACT:
A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, intergate dielectric layer, tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. The second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are under the first stacked gate structure, and the source/drain regions are in the exposed substrate.

REFERENCES:
patent: 6248631 (2001-06-01), Huang et al.

Affiliated with

Also associated with

Rating

NAND flash memory cell row does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with NAND flash memory cell row, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NAND flash memory cell row will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3704774