Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2003-01-10
2004-11-02
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S200000, C365S238500
Reexamination Certificate
active
06813184
ABSTRACT:
This application claims priority from Korean Patent Application No. 2002-1875, filed on Jan. 12, 2002, the contents of which are herein incorporated by reference in their entirety for all purposes.
TECHNICAL FIELD
This disclosure generally relates to semiconductor memories, and more specifically, to a NAND flash memory having verifying functions for data bits held in page buffers during operation modes of programming, erasing, and copy-back programming.
BACKGROUND
A NAND flash memory, a kind of nonvolatile memory, employs page buffers for latching data (i.e., page data) assigned to a selected page during a read operation, which is referred to as a “sensing operation” of the page buffers, while storing data (i.e., program data) supplied from the external during a programming operation, which is referred to as a “data loading operation” of the page buffers. Further, the page buffers contribute to prevent program-inhibited cells or programmed cells from being programmed undesirably. When a verifying operation that is checking whether a memory cell is programmed or erased reaches its target (or desired) threshold voltage level, the page buffers detect data bits of memory cells of a selected page, and latch those voltage values. Then, the page buffers provide their data bits into a pass/fail check circuit to confirm those data bits are pass data bits informing of an successive programming or erasing.
Such page buffers have been disclosed in U.S. Pat. No. 5,790,458 entitled “Sense amplifier for nonvolatile semiconductor memory device”, U.S. Pat. No. 5,761,132 entitled “Integrated circuit memory devices with latch-free page buffers therein for preventing read failures”, and U.S. Pat. No. 5,712,818 entitled “Data loading circuit for partial program of nonvolatile semiconductor memory”.
One of the known page buffers is shown in FIG.
1
. The page buffer of
FIG. 1
is connected to a pair of bitlines BLe and BLo, including a pair of latches LAT
1
and LAT
2
(main and cache). NMOS transistors M
1
~M
4
form a bitline selection and biasing circuit, which connects one of the bitlines to a sensing node SO and causes the other bitline to be in a floating state. Between the bitline BLe and a sensing node SO is an NMOS transistor M
1
that responds to a control signal BLSHFe. Between the bitline BLo and the sensing node SO is an NMOS transistor M
2
that responds to a control signal BLSHFo. An NMOS transistor M
3
is connected between the bitline BLe and a control signal line VIRPWR and an NMOS transistor M
4
between BLo and VIRPWR. The NMOS transistors M
3
and M
4
respond to control signals VBLe and VBLo, respectively. The transistors M
1
~M
4
form a bitline selection and biasing circuit to connect one of the bitlines to the sensing node SO and causes the other bitline be in a floating state.
Between a power supply voltage VCC and the sensing node SO is a PMOS transistor M
5
that responds to a control signal PLOAD. A PMOS transistor M
6
is connected between VCC and a main latch node nB of the main latch LAT
1
, controlled by a signal PBRST. Between the latch node nB and a ground voltage VSS are NMOS transistors M
7
and M
8
, in series, responding to a voltage level of the sensing node SO and a control signal PBLHCM, respectively. A PMOS transistor M
9
is connected between VCC and an output terminal nWDO, being turned on or off responsively to a logic state of a main latch node B. The output terminal nWDO is led to a pass/fail check circuit shown in
FIG. 2. A
logic state of the output terminal nWDO is complementary to that of the main latch node B. For instance, the output terminal nWDO is connected to VCC when the main latch node B has a low level. Otherwise, the output terminal nWDO is electrically isolated from VCC, in a floating state, when the main latch node B is set at a high level.
An NMOs transistor M
10
connected between the sensing node SO and the main latch node B of the main latch LAT
1
responds to the signal BLSLT. Between an internal node ND
1
and the main latch node B is an NMOS transistor M
11
responding to a signal PBDO. A PMOS transistor M
12
is connected between VCC and a cache latch node A of the cache latch LAT
2
, responding to a signal PBSET. An NMOS transistor M
13
is connected between the cache latch node A and the sensing node SO, responding to a signal PDUMP. Between the main latch node A and VSS are NMOS transistors M
14
and M
15
in series. The NMOS transistors M
14
and M
15
respond to a logic state of the sensing node SO and a signal PBLCHC respectively. Between the internal node ND
1
and a cache latch node nA (a counter node of A) of the cache latch LAT
2
is an NMOS transistor M
16
and between the internal node ND
1
and the cache latch node A is connected to an NMOS transistor M
17
. The NMOS transistors M
16
and M
17
respond to data signals DLi and nDLi, complementary to each other, respectively.
When a program data bit is “1” (as a binary code) to be loaded in the page buffer circuit of
FIG. 1
, the data signal DLi is logically set to a high level while the data signal nDLi is established at a low level. The internal node ND
1
is connected to a data line DLi through NMOS transistors M
18
and M
19
those form a column gate circuit responding to column selection signals YA and YB respectively. Between the data line DLi and the ground voltage is an NMOS transistor M
20
, responding to a signal DLD.
The page buffer shown in
FIG. 1
is operable in erasing, programming, reading, and copy-back programming modes. The copy-back programming is referred to an operation of moving data stored in a page into another page, having been proposed in U.S. Pat. No. 5,996,041 entitled “Integrated circuit memory devices having page flag cells which indicate the true of non-true state of page data therein and methods of operating the same”.
In programming with the page buffer of
FIG. 1
, a program data bit is loaded into the latch LAT
2
. For instance, if a program data bit is “1”, a data signal DLi becomes a high level while a data signal nDLi becomes a low level. The NMOS transistor M
16
is turned on while an NMOS transistor M
17
is turned off. At the same time, NMOS transistors M
18
and M
19
are turned on by column selection signals YA and YB, thereby connecting the latch node nA to the data line DLi through M
18
and M
19
. For loading the program data bit, the data line DLi is connected to a ground voltage through the NMOS transistor M
20
. Thus, the program data bit of “1” is loaded into the latch node A. If a program data bit is “0”, the data signal DLi becomes a low level while the data signal nDLi becomes a high level. As the NMOS transistor M
17
connects the latch node A to the data line DLi that is at the ground voltage, the program data bit “0” is loaded into the latch node A. Through the aforementioned procedure, all program data bits are loaded into the page buffers in sequence.
After completing the loading operation of the program data bit into the cache latch LAT
2
, the data bit is transferred to the main latch LAT
1
. First, the main latch LAT
1
is initiated by a turn-on of an NMOS transistor M
6
and the sensing node SO is charged up to a high level by a PMOS transistor M
5
. And then, an NMOS transistor M
13
is turned on to transfer the program data bit from LAT
2
to LAT
1
. If the program data bit of “1” has been loaded in the cache latch LAT
2
, it is latched at a node B of LAT
1
when NMOS transistors M
7
and M
8
are turned on. On the contrary, when the program data bit of “0” is loaded in the cache latch LAT
2
, the NMOS transistor M
7
is turned off and thereby the node B of LAT
1
maintains its initial state regardless of a turn-on of the NMOS transistor M
8
by a control signal PBLCHM.
The program data bit loaded in the main latch LAT
1
is put into a program operation for a selected bitline for which a selected memory cell will be programmed, while the other non-selected memory cells will be program-inhibited. During programming with the data bit held in the main latch LAT
1
, the cache latch LAT
2
as a cache bri
Lam David
Marger Johnson & McColom, P.C.
Samsung Electronics Co,. Ltd.
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