NAND-cell type electrically erasable and programmable read-only

Details NAND-cell type electrically erasable and programmable read-only NAND-cell type electrically erasable and programmable read-only

1992-10-14

1994-01-11

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

365185, 36523003, G11C 1140, G11C 502

Patent

active

052787940

ABSTRACT:
A NAND-cell type electrically erasable and programmable read only memory includes an array of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field effect transistor having a floating gate and an insulated control gate. The memory cell array is divided into a plurality of cell blocks, each of which includes NAND cell sections each including a predetermined number of a series-connected memory cell transistors. A redundancy cell section is provided which includes an array of redundancy memory cells containing at least one spare cell block. A row redundancy circuit is connected to a row decoder, and is responsive to an address buffer. The redundancy circuit replaces a defective block containing a defective memory cell or cells with the spare cell block.

REFERENCES:
patent: 5075890 (1991-12-01), Itoh et al.
patent: 5220518 (1993-06-01), Haq

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