N-well resistor as a ballast resistor for output MOSFET

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257336, 257355, 257357, 257363, H01L 2776, H01L 2994, H01L 2701, H01L 31062

Patent

active

056379021

ABSTRACT:
A resistor formed in a well adjacent to a transistor serves as a ballast resistor for the transistor. The transistor is formed in a first region on a substrate. The first region is of a first conductivity type. A well of second conductivity type is formed adjacent to the first region. A gate region is formed over a portion of the first region. Concurrently, a covering is formed over a first area of the well. The covering and the gate region are comprised of the same material. Source/drain regions of the second conductivity type are formed on either side of the gate region. The source/drain regions are of the first conductivity type. A first source/drain region extends into the well. Concurrent to the forming of the source drain regions, a doped region is formed within the well. The doped region and the first source/drain region have the same doping density. The doped region is physically separated from the first source/drain region by the first area of the well. Contact regions for the transistor are formed within the second source/drain region and within the doped region.

REFERENCES:
patent: 4937471 (1990-06-01), Park et al.
patent: 5440162 (1995-08-01), Worley et al.
T. Polgreen, et al., Improving the ESD Failure Threshold of Silicided nMOS Output Transistors by Ensuring Uniform Current Flow, Proceedings. of EOS/ESD Symp., 1989, pp. 167-174.
C.H. Diaz, et al, Building-in ESD/EOS Reliability for Sub-halfmicron CMOS Processes, IRPS, 1995, pp. 276-283.
A. Amerasekera, et al, Characterization and Modeling of Second Breakdown in NMOST's for the Extraction of ESD-Related Process and Design Parameters, IEEE Tran. Ele. Dev. vol. ED-38, pp. 2161-2168, Sep. 1991.

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