N-way set-associative external cache with standard DDR...

Details N-way set-associative external cache with standard DDR... N-way set-associative external cache with standard DDR...

2005-06-28

2005-06-28

Vital, Pierre M. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S128000, C711S154000

Reexamination Certificate

active

06912628

ABSTRACT:
A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory devices. The set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags.

REFERENCES:
patent: 4493026 (1985-01-01), Olnowich
patent: 5893146 (1999-04-01), Pickett
patent: 6226707 (2001-05-01), Mattela et al.
patent: 6681299 (2004-01-01), Shimamura et al.
patent: 0095033 (1983-11-01), None

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